950 lines
28 KiB
C
950 lines
28 KiB
C
/*
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* PMC-Sierra MSP board specific pci_ops
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*
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* Copyright 2001 MontaVista Software Inc.
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* Copyright 2005-2007 PMC-Sierra, Inc
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*
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Much of the code is derived from the original DDB5074 port by
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* Geert Uytterhoeven <geert@linux-m68k.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#define PCI_COUNTERS 1
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/byteorder.h>
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#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
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#include <asm/mipsmtregs.h>
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#endif
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#include <msp_prom.h>
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#include <msp_cic_int.h>
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#include <msp_pci.h>
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#include <msp_regs.h>
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#include <msp_regops.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
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static char proc_init;
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extern struct proc_dir_entry *proc_bus_pci_dir;
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unsigned int pci_int_count[32];
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static void pci_proc_init(void);
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/*****************************************************************************
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*
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* FUNCTION: show_msp_pci_counts
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* _________________________________________________________________________
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*
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* DESCRIPTION: Prints the count of how many times each PCI
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* interrupt has asserted. Can be invoked by the
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* /proc filesystem.
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*
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* INPUTS: m - synthetic file construction data
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* v - iterator
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*
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* RETURNS: 0 or error
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*
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****************************************************************************/
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static int show_msp_pci_counts(struct seq_file *m, void *v)
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{
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int i;
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unsigned int intcount, total = 0;
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for (i = 0; i < 32; ++i) {
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intcount = pci_int_count[i];
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if (intcount != 0) {
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seq_printf(m, "[%d] = %u\n", i, intcount);
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total += intcount;
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}
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}
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seq_printf(m, "total = %u\n", total);
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return 0;
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}
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/*****************************************************************************
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*
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* FUNCTION: gen_pci_cfg_wr_show
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* _________________________________________________________________________
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*
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* DESCRIPTION: Generates a configuration write cycle for debug purposes.
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* The IDSEL line asserted and location and data written are
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* immaterial. Just want to be able to prove that a
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* configuration write can be correctly generated on the
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* PCI bus. Intent is that this function by invocable from
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* the /proc filesystem.
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*
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* INPUTS: m - synthetic file construction data
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* v - iterator
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*
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* RETURNS: 0 or error
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*
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****************************************************************************/
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static int gen_pci_cfg_wr_show(struct seq_file *m, void *v)
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{
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unsigned char where = 0; /* Write to static Device/Vendor ID */
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unsigned char bus_num = 0; /* Bus 0 */
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unsigned char dev_fn = 0xF; /* Arbitrary device number */
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u32 wr_data = 0xFF00AA00; /* Arbitrary data */
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struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
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unsigned long value;
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int intr;
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seq_puts(m, "PMC MSP PCI: Beginning\n");
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if (proc_init == 0) {
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pci_proc_init();
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proc_init = ~0;
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}
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seq_puts(m, "PMC MSP PCI: Before Cfg Wr\n");
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/*
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* Generate PCI Configuration Write Cycle
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*/
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/* Clear cause register bits */
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preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
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/* Setup address that is to appear on PCI bus */
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preg->config_addr = BPCI_CFGADDR_ENABLE |
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(bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
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(dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
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(where & 0xFC);
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value = cpu_to_le32(wr_data);
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/* Launch the PCI configuration write cycle */
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*PCI_CONFIG_SPACE_REG = value;
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/*
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* Check if the PCI configuration cycle (rd or wr) succeeded, by
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* checking the status bits for errors like master or target abort.
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*/
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intr = preg->if_status;
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seq_puts(m, "PMC MSP PCI: After Cfg Wr\n");
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return 0;
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}
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/*****************************************************************************
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*
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* FUNCTION: pci_proc_init
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* _________________________________________________________________________
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*
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* DESCRIPTION: Create entries in the /proc filesystem for debug access.
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*
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* INPUTS: none
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*
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* OUTPUTS: none
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*
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* RETURNS: none
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*
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****************************************************************************/
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static void pci_proc_init(void)
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{
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proc_create_single("pmc_msp_pci_rd_cnt", 0, NULL, show_msp_pci_counts);
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proc_create_single("pmc_msp_pci_cfg_wr", 0, NULL, gen_pci_cfg_wr_show);
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}
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#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
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/*****************************************************************************
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*
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* STRUCT: pci_io_resource
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* _________________________________________________________________________
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*
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* DESCRIPTION: Defines the address range that pciauto() will use to
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* assign to the I/O BARs of PCI devices.
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*
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* Use the start and end addresses of the MSP7120 PCI Host
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* Controller I/O space, in the form that they appear on the
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* PCI bus AFTER MSP7120 has performed address translation.
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*
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* For I/O accesses, MSP7120 ignores OATRAN and maps I/O
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* accesses into the bottom 0xFFF region of address space,
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* so that is the range to put into the pci_io_resource
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* struct.
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*
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* In MSP4200, the start address was 0x04 instead of the
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* expected 0x00. Will just assume there was a good reason
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* for this!
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*
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* NOTES: Linux, by default, will assign I/O space to the lowest
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* region of address space. Since MSP7120 and Linux,
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* by default, have no offset in between how they map, the
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* io_offset element of pci_controller struct should be set
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* to zero.
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* ELEMENTS:
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* name - String used for a meaningful name.
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*
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* start - Start address of MSP7120's I/O space, as MSP7120 presents
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* the address on the PCI bus.
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*
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* end - End address of MSP7120's I/O space, as MSP7120 presents
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* the address on the PCI bus.
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*
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* flags - Attributes indicating the type of resource. In this case,
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* indicate I/O space.
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*
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****************************************************************************/
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static struct resource pci_io_resource = {
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.name = "pci IO space",
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.start = 0x04,
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.end = 0x0FFF,
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.flags = IORESOURCE_IO /* I/O space */
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};
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/*****************************************************************************
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*
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* STRUCT: pci_mem_resource
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* _________________________________________________________________________
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*
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* DESCRIPTION: Defines the address range that pciauto() will use to
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* assign to the memory BARs of PCI devices.
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*
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* The .start and .end values are dependent upon how address
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* translation is performed by the OATRAN regiser.
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*
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* The values to use for .start and .end are the values
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* in the form they appear on the PCI bus AFTER MSP7120 has
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* performed OATRAN address translation.
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*
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* ELEMENTS:
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* name - String used for a meaningful name.
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*
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* start - Start address of MSP7120's memory space, as MSP7120 presents
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* the address on the PCI bus.
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*
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* end - End address of MSP7120's memory space, as MSP7120 presents
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* the address on the PCI bus.
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*
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* flags - Attributes indicating the type of resource. In this case,
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* indicate memory space.
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*
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****************************************************************************/
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static struct resource pci_mem_resource = {
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.name = "pci memory space",
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.start = MSP_PCI_SPACE_BASE,
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.end = MSP_PCI_SPACE_END,
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.flags = IORESOURCE_MEM /* memory space */
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};
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/*****************************************************************************
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*
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* FUNCTION: bpci_interrupt
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* _________________________________________________________________________
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*
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* DESCRIPTION: PCI status interrupt handler. Updates the count of how
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* many times each status bit has been set, then clears
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* the status bits. If the appropriate macros are defined,
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* these counts can be viewed via the /proc filesystem.
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*
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* INPUTS: irq - unused
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* dev_id - unused
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* pt_regs - unused
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*
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* OUTPUTS: none
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*
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* RETURNS: PCIBIOS_SUCCESSFUL - success
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*
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****************************************************************************/
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static irqreturn_t bpci_interrupt(int irq, void *dev_id)
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{
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struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
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unsigned int stat = preg->if_status;
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#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
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int i;
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for (i = 0; i < 32; ++i) {
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if ((1 << i) & stat)
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++pci_int_count[i];
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}
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#endif /* PROC_FS && PCI_COUNTERS */
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/* printk("PCI ISR: Status=%08X\n", stat); */
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/* write to clear all asserted interrupts */
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preg->if_status = stat;
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return IRQ_HANDLED;
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}
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/*****************************************************************************
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*
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* FUNCTION: msp_pcibios_config_access
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* _________________________________________________________________________
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*
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* DESCRIPTION: Performs a PCI configuration access (rd or wr), then
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* checks that the access succeeded by querying MSP7120's
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* PCI status bits.
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*
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* INPUTS:
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* access_type - kind of PCI configuration cycle to perform
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* (read or write). Legal values are
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* PCI_ACCESS_WRITE and PCI_ACCESS_READ.
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*
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* bus - pointer to the bus number of the device to
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* be targeted for the configuration cycle.
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* The only element of the pci_bus structure
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* used is bus->number. This argument determines
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* if the configuration access will be Type 0 or
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* Type 1. Since MSP7120 assumes itself to be the
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* PCI Host, any non-zero bus->number generates
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* a Type 1 access.
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*
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* devfn - this is an 8-bit field. The lower three bits
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* specify the function number of the device to
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* be targeted for the configuration cycle, with
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* all three-bit combinations being legal. The
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* upper five bits specify the device number,
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* with legal values being 10 to 31.
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*
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* where - address within the Configuration Header
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* space to access.
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*
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* data - for write accesses, contains the data to
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* write.
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*
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* OUTPUTS:
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* data - for read accesses, contains the value read.
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*
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* RETURNS: PCIBIOS_SUCCESSFUL - success
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* -1 - access failure
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*
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****************************************************************************/
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int msp_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus,
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unsigned int devfn,
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unsigned char where,
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u32 *data)
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{
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struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
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unsigned char bus_num = bus->number;
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unsigned char dev_fn = (unsigned char)devfn;
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unsigned long intr;
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unsigned long value;
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static char pciirqflag;
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int ret;
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#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
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unsigned int vpe_status;
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#endif
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#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
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if (proc_init == 0) {
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pci_proc_init();
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proc_init = ~0;
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}
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#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
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/*
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* Just the first time this function invokes, allocate
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* an interrupt line for PCI host status interrupts. The
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* allocation assigns an interrupt handler to the interrupt.
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*/
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if (pciirqflag == 0) {
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ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
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bpci_interrupt,
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IRQF_SHARED,
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"PMC MSP PCI Host",
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preg);
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if (ret != 0)
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return ret;
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pciirqflag = ~0;
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}
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#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
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vpe_status = dvpe();
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#endif
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/*
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* Clear PCI cause register bits.
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*
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* In Polo, the PCI Host had a dedicated DMA called the
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* Block Copy (not to be confused with the general purpose Block
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* Copy Engine block). There appear to have been special interrupts
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* for this Block Copy, called Block Copy 0 Fault (BC0F) and
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* Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
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* dedicated Block Copy block, so these two interrupts are now
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* marked reserved. In case the Block Copy is resurrected in a
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* future design, maintain the code that treats these two interrupts
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* specially.
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*
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* Write to clear all interrupts in the PCI status register, aside
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* from BC0F and BC1F.
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*/
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preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
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/* Setup address that is to appear on PCI bus */
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preg->config_addr = BPCI_CFGADDR_ENABLE |
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(bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
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(dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
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(where & 0xFC);
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/* IF access is a PCI configuration write */
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if (access_type == PCI_ACCESS_WRITE) {
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value = cpu_to_le32(*data);
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*PCI_CONFIG_SPACE_REG = value;
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} else {
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/* ELSE access is a PCI configuration read */
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value = le32_to_cpu(*PCI_CONFIG_SPACE_REG);
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*data = value;
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}
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/*
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* Check if the PCI configuration cycle (rd or wr) succeeded, by
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* checking the status bits for errors like master or target abort.
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*/
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intr = preg->if_status;
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/* Clear config access */
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preg->config_addr = 0;
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/* IF error occurred */
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if (intr & ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F)) {
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/* Clear status bits */
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preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
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#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
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evpe(vpe_status);
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#endif
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return -1;
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}
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#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
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evpe(vpe_status);
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#endif
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return PCIBIOS_SUCCESSFUL;
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}
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/*****************************************************************************
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*
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* FUNCTION: msp_pcibios_read_config_byte
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* _________________________________________________________________________
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*
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* DESCRIPTION: Read a byte from PCI configuration address spac
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* Since the hardware can't address 8 bit chunks
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* directly, read a 32-bit chunk, then mask off extraneous
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* bits.
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*
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* INPUTS bus - structure containing attributes for the PCI bus
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* that the read is destined for.
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* devfn - device/function combination that the read is
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* destined for.
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* where - register within the Configuration Header space
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* to access.
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*
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* OUTPUTS val - read data
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*
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* RETURNS: PCIBIOS_SUCCESSFUL - success
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* -1 - read access failure
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*
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****************************************************************************/
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static int
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msp_pcibios_read_config_byte(struct pci_bus *bus,
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unsigned int devfn,
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int where,
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u32 *val)
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{
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u32 data = 0;
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/*
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* If the config access did not complete normally (e.g., underwent
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* master abort) do the PCI compliant thing, which is to supply an
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* all ones value.
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*/
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if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
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where, &data)) {
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*val = 0xFFFFFFFF;
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return -1;
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}
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*val = (data >> ((where & 3) << 3)) & 0x0ff;
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return PCIBIOS_SUCCESSFUL;
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}
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/*****************************************************************************
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*
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* FUNCTION: msp_pcibios_read_config_word
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* _________________________________________________________________________
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*
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* DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
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* Since the hardware can't address 16 bit chunks
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* directly, read a 32-bit chunk, then mask off extraneous
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* bits.
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*
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* INPUTS bus - structure containing attributes for the PCI bus
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* that the read is destined for.
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* devfn - device/function combination that the read is
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* destined for.
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* where - register within the Configuration Header space
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* to access.
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*
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* OUTPUTS val - read data
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*
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* RETURNS: PCIBIOS_SUCCESSFUL - success
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* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
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* -1 - read access failure
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*
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****************************************************************************/
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static int
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msp_pcibios_read_config_word(struct pci_bus *bus,
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unsigned int devfn,
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int where,
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u32 *val)
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{
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u32 data = 0;
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/* if (where & 1) */ /* Commented out non-compliant code.
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* Should allow word access to configuration
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* registers, with only exception being when
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* the word access would wrap around into
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* the next dword.
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*/
|
|
if ((where & 3) == 3) {
|
|
*val = 0xFFFFFFFF;
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
}
|
|
|
|
/*
|
|
* If the config access did not complete normally (e.g., underwent
|
|
* master abort) do the PCI compliant thing, which is to supply an
|
|
* all ones value.
|
|
*/
|
|
if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
|
|
where, &data)) {
|
|
*val = 0xFFFFFFFF;
|
|
return -1;
|
|
}
|
|
|
|
*val = (data >> ((where & 3) << 3)) & 0x0ffff;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* FUNCTION: msp_pcibios_read_config_dword
|
|
* _________________________________________________________________________
|
|
*
|
|
* DESCRIPTION: Read a double word (32 bits) from PCI configuration
|
|
* address space.
|
|
*
|
|
* INPUTS bus - structure containing attributes for the PCI bus
|
|
* that the read is destined for.
|
|
* devfn - device/function combination that the read is
|
|
* destined for.
|
|
* where - register within the Configuration Header space
|
|
* to access.
|
|
*
|
|
* OUTPUTS val - read data
|
|
*
|
|
* RETURNS: PCIBIOS_SUCCESSFUL - success
|
|
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
|
|
* -1 - read access failure
|
|
*
|
|
****************************************************************************/
|
|
static int
|
|
msp_pcibios_read_config_dword(struct pci_bus *bus,
|
|
unsigned int devfn,
|
|
int where,
|
|
u32 *val)
|
|
{
|
|
u32 data = 0;
|
|
|
|
/* Address must be dword aligned. */
|
|
if (where & 3) {
|
|
*val = 0xFFFFFFFF;
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
}
|
|
|
|
/*
|
|
* If the config access did not complete normally (e.g., underwent
|
|
* master abort) do the PCI compliant thing, which is to supply an
|
|
* all ones value.
|
|
*/
|
|
if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
|
|
where, &data)) {
|
|
*val = 0xFFFFFFFF;
|
|
return -1;
|
|
}
|
|
|
|
*val = data;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* FUNCTION: msp_pcibios_write_config_byte
|
|
* _________________________________________________________________________
|
|
*
|
|
* DESCRIPTION: Write a byte to PCI configuration address space.
|
|
* Since the hardware can't address 8 bit chunks
|
|
* directly, a read-modify-write is performed.
|
|
*
|
|
* INPUTS bus - structure containing attributes for the PCI bus
|
|
* that the write is destined for.
|
|
* devfn - device/function combination that the write is
|
|
* destined for.
|
|
* where - register within the Configuration Header space
|
|
* to access.
|
|
* val - value to write
|
|
*
|
|
* OUTPUTS none
|
|
*
|
|
* RETURNS: PCIBIOS_SUCCESSFUL - success
|
|
* -1 - write access failure
|
|
*
|
|
****************************************************************************/
|
|
static int
|
|
msp_pcibios_write_config_byte(struct pci_bus *bus,
|
|
unsigned int devfn,
|
|
int where,
|
|
u8 val)
|
|
{
|
|
u32 data = 0;
|
|
|
|
/* read config space */
|
|
if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
|
|
where, &data))
|
|
return -1;
|
|
|
|
/* modify the byte within the dword */
|
|
data = (data & ~(0xff << ((where & 3) << 3))) |
|
|
(val << ((where & 3) << 3));
|
|
|
|
/* write back the full dword */
|
|
if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
|
|
where, &data))
|
|
return -1;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* FUNCTION: msp_pcibios_write_config_word
|
|
* _________________________________________________________________________
|
|
*
|
|
* DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
|
|
* Since the hardware can't address 16 bit chunks
|
|
* directly, a read-modify-write is performed.
|
|
*
|
|
* INPUTS bus - structure containing attributes for the PCI bus
|
|
* that the write is destined for.
|
|
* devfn - device/function combination that the write is
|
|
* destined for.
|
|
* where - register within the Configuration Header space
|
|
* to access.
|
|
* val - value to write
|
|
*
|
|
* OUTPUTS none
|
|
*
|
|
* RETURNS: PCIBIOS_SUCCESSFUL - success
|
|
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
|
|
* -1 - write access failure
|
|
*
|
|
****************************************************************************/
|
|
static int
|
|
msp_pcibios_write_config_word(struct pci_bus *bus,
|
|
unsigned int devfn,
|
|
int where,
|
|
u16 val)
|
|
{
|
|
u32 data = 0;
|
|
|
|
/* Fixed non-compliance: if (where & 1) */
|
|
if ((where & 3) == 3)
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
/* read config space */
|
|
if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
|
|
where, &data))
|
|
return -1;
|
|
|
|
/* modify the word within the dword */
|
|
data = (data & ~(0xffff << ((where & 3) << 3))) |
|
|
(val << ((where & 3) << 3));
|
|
|
|
/* write back the full dword */
|
|
if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
|
|
where, &data))
|
|
return -1;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* FUNCTION: msp_pcibios_write_config_dword
|
|
* _________________________________________________________________________
|
|
*
|
|
* DESCRIPTION: Write a double word (32-bits) to PCI configuration address
|
|
* space.
|
|
*
|
|
* INPUTS bus - structure containing attributes for the PCI bus
|
|
* that the write is destined for.
|
|
* devfn - device/function combination that the write is
|
|
* destined for.
|
|
* where - register within the Configuration Header space
|
|
* to access.
|
|
* val - value to write
|
|
*
|
|
* OUTPUTS none
|
|
*
|
|
* RETURNS: PCIBIOS_SUCCESSFUL - success
|
|
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
|
|
* -1 - write access failure
|
|
*
|
|
****************************************************************************/
|
|
static int
|
|
msp_pcibios_write_config_dword(struct pci_bus *bus,
|
|
unsigned int devfn,
|
|
int where,
|
|
u32 val)
|
|
{
|
|
/* check that address is dword aligned */
|
|
if (where & 3)
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
/* perform write */
|
|
if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
|
|
where, &val))
|
|
return -1;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* FUNCTION: msp_pcibios_read_config
|
|
* _________________________________________________________________________
|
|
*
|
|
* DESCRIPTION: Interface the PCI configuration read request with
|
|
* the appropriate function, based on how many bytes
|
|
* the read request is.
|
|
*
|
|
* INPUTS bus - structure containing attributes for the PCI bus
|
|
* that the write is destined for.
|
|
* devfn - device/function combination that the write is
|
|
* destined for.
|
|
* where - register within the Configuration Header space
|
|
* to access.
|
|
* size - in units of bytes, should be 1, 2, or 4.
|
|
*
|
|
* OUTPUTS val - value read, with any extraneous bytes masked
|
|
* to zero.
|
|
*
|
|
* RETURNS: PCIBIOS_SUCCESSFUL - success
|
|
* -1 - failure
|
|
*
|
|
****************************************************************************/
|
|
int
|
|
msp_pcibios_read_config(struct pci_bus *bus,
|
|
unsigned int devfn,
|
|
int where,
|
|
int size,
|
|
u32 *val)
|
|
{
|
|
if (size == 1) {
|
|
if (msp_pcibios_read_config_byte(bus, devfn, where, val)) {
|
|
return -1;
|
|
}
|
|
} else if (size == 2) {
|
|
if (msp_pcibios_read_config_word(bus, devfn, where, val)) {
|
|
return -1;
|
|
}
|
|
} else if (size == 4) {
|
|
if (msp_pcibios_read_config_dword(bus, devfn, where, val)) {
|
|
return -1;
|
|
}
|
|
} else {
|
|
*val = 0xFFFFFFFF;
|
|
return -1;
|
|
}
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* FUNCTION: msp_pcibios_write_config
|
|
* _________________________________________________________________________
|
|
*
|
|
* DESCRIPTION: Interface the PCI configuration write request with
|
|
* the appropriate function, based on how many bytes
|
|
* the read request is.
|
|
*
|
|
* INPUTS bus - structure containing attributes for the PCI bus
|
|
* that the write is destined for.
|
|
* devfn - device/function combination that the write is
|
|
* destined for.
|
|
* where - register within the Configuration Header space
|
|
* to access.
|
|
* size - in units of bytes, should be 1, 2, or 4.
|
|
* val - value to write
|
|
*
|
|
* OUTPUTS: none
|
|
*
|
|
* RETURNS: PCIBIOS_SUCCESSFUL - success
|
|
* -1 - failure
|
|
*
|
|
****************************************************************************/
|
|
int
|
|
msp_pcibios_write_config(struct pci_bus *bus,
|
|
unsigned int devfn,
|
|
int where,
|
|
int size,
|
|
u32 val)
|
|
{
|
|
if (size == 1) {
|
|
if (msp_pcibios_write_config_byte(bus, devfn,
|
|
where, (u8)(0xFF & val))) {
|
|
return -1;
|
|
}
|
|
} else if (size == 2) {
|
|
if (msp_pcibios_write_config_word(bus, devfn,
|
|
where, (u16)(0xFFFF & val))) {
|
|
return -1;
|
|
}
|
|
} else if (size == 4) {
|
|
if (msp_pcibios_write_config_dword(bus, devfn, where, val)) {
|
|
return -1;
|
|
}
|
|
} else {
|
|
return -1;
|
|
}
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* STRUCTURE: msp_pci_ops
|
|
* _________________________________________________________________________
|
|
*
|
|
* DESCRIPTION: structure to abstract the hardware specific PCI
|
|
* configuration accesses.
|
|
*
|
|
* ELEMENTS:
|
|
* read - function for Linux to generate PCI Configuration reads.
|
|
* write - function for Linux to generate PCI Configuration writes.
|
|
*
|
|
****************************************************************************/
|
|
struct pci_ops msp_pci_ops = {
|
|
.read = msp_pcibios_read_config,
|
|
.write = msp_pcibios_write_config
|
|
};
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* STRUCTURE: msp_pci_controller
|
|
* _________________________________________________________________________
|
|
*
|
|
* Describes the attributes of the MSP7120 PCI Host Controller
|
|
*
|
|
* ELEMENTS:
|
|
* pci_ops - abstracts the hardware specific PCI configuration
|
|
* accesses.
|
|
*
|
|
* mem_resource - address range pciauto() uses to assign to PCI device
|
|
* memory BARs.
|
|
*
|
|
* mem_offset - offset between how MSP7120 outbound PCI memory
|
|
* transaction addresses appear on the PCI bus and how Linux
|
|
* wants to configure memory BARs of the PCI devices.
|
|
* MSP7120 does nothing funky, so just set to zero.
|
|
*
|
|
* io_resource - address range pciauto() uses to assign to PCI device
|
|
* I/O BARs.
|
|
*
|
|
* io_offset - offset between how MSP7120 outbound PCI I/O
|
|
* transaction addresses appear on the PCI bus and how
|
|
* Linux defaults to configure I/O BARs of the PCI devices.
|
|
* MSP7120 maps outbound I/O accesses into the bottom
|
|
* bottom 4K of PCI address space (and ignores OATRAN).
|
|
* Since the Linux default is to configure I/O BARs to the
|
|
* bottom 4K, no special offset is needed. Just set to zero.
|
|
*
|
|
****************************************************************************/
|
|
static struct pci_controller msp_pci_controller = {
|
|
.pci_ops = &msp_pci_ops,
|
|
.mem_resource = &pci_mem_resource,
|
|
.mem_offset = 0,
|
|
.io_map_base = MSP_PCI_IOSPACE_BASE,
|
|
.io_resource = &pci_io_resource,
|
|
.io_offset = 0
|
|
};
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* FUNCTION: msp_pci_init
|
|
* _________________________________________________________________________
|
|
*
|
|
* DESCRIPTION: Initialize the PCI Host Controller and register it with
|
|
* Linux so Linux can seize control of the PCI bus.
|
|
*
|
|
****************************************************************************/
|
|
void __init msp_pci_init(void)
|
|
{
|
|
struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
|
|
u32 id;
|
|
|
|
/* Extract Device ID */
|
|
id = read_reg32(PCI_JTAG_DEVID_REG, 0xFFFF) >> 12;
|
|
|
|
/* Check if JTAG ID identifies MSP7120 */
|
|
if (!MSP_HAS_PCI(id)) {
|
|
printk(KERN_WARNING "PCI: No PCI; id reads as %x\n", id);
|
|
goto no_pci;
|
|
}
|
|
|
|
/*
|
|
* Enable flushing of the PCI-SDRAM queue upon a read
|
|
* of the SDRAM's Memory Configuration Register.
|
|
*/
|
|
*(unsigned long *)QFLUSH_REG_1 = 3;
|
|
|
|
/* Configure PCI Host Controller. */
|
|
preg->if_status = ~0; /* Clear cause register bits */
|
|
preg->config_addr = 0; /* Clear config access */
|
|
preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */
|
|
preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */
|
|
|
|
/* configure so inb(), outb(), and family are functional */
|
|
set_io_port_base(MSP_PCI_IOSPACE_BASE);
|
|
|
|
/* Tell Linux the details of the MSP7120 PCI Host Controller */
|
|
register_pci_controller(&msp_pci_controller);
|
|
|
|
return;
|
|
|
|
no_pci:
|
|
/* Disable PCI channel */
|
|
printk(KERN_WARNING "PCI: no host PCI bus detected\n");
|
|
}
|