83 lines
2 KiB
C
83 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#ifndef _ASM_NDS32_NDS32_H_
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#define _ASM_NDS32_NDS32_H_
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#include <asm/bitfield.h>
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#include <asm/cachectl.h>
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#ifndef __ASSEMBLY__
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#include <linux/init.h>
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#include <asm/barrier.h>
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#include <nds32_intrinsic.h>
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#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
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#define FP_OFFSET (-3)
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#else
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#define FP_OFFSET (-2)
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#endif
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#define LP_OFFSET (-1)
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extern void __init early_trap_init(void);
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static inline void GIE_ENABLE(void)
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{
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mb();
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__nds32__gie_en();
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}
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static inline void GIE_DISABLE(void)
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{
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mb();
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__nds32__gie_dis();
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}
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static inline unsigned long CACHE_SET(unsigned char cache)
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{
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if (cache == ICACHE)
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return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>
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ICM_CFG_offISET);
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else
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return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>
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DCM_CFG_offDSET);
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}
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static inline unsigned long CACHE_WAY(unsigned char cache)
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{
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if (cache == ICACHE)
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return 1 +
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((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
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else
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return 1 +
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((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
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}
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static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)
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{
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if (cache == ICACHE)
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return 8 <<
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(((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
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else
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return 8 <<
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(((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
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}
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#endif /* __ASSEMBLY__ */
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#define IVB_BASE PHYS_OFFSET /* in user space for intr/exc/trap/break table base, 64KB aligned
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* We defined at the start of the physical memory */
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/* dispatched sub-entry exception handler numbering */
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#define RD_PROT 0 /* read protrection */
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#define WRT_PROT 1 /* write protection */
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#define NOEXEC 2 /* non executable */
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#define PAGE_MODIFY 3 /* page modified */
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#define ACC_BIT 4 /* access bit */
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#define RESVED_PTE 5 /* reserved PTE attribute */
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/* reserved 6 ~ 16 */
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#endif /* _ASM_NDS32_NDS32_H_ */
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