156 lines
4.2 KiB
C
156 lines
4.2 KiB
C
/*
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* arch/sh/kernel/cpu/sh4/clock-sh7757.c
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*
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* SH7757 support for the clock framework
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*
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* Copyright (C) 2009-2010 Renesas Solutions Corp.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.rate = 48000000,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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int multiplier;
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multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
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return clk->parent->rate * multiplier;
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}
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static struct sh_clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk *clks[] = {
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&extal_clk,
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&pll_clk,
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};
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static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
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1, 1, 1, 16, 1, 24, 1, 1 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
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#define DIV4(_bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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/*
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* P clock is always enable, because some P clock modules is used
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* by Host PC.
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*/
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[DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0 0xffc80030
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#define MSTPCR1 0xffc80034
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#define MSTPCR2 0xffc10028
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enum { MSTP004, MSTP000, MSTP127, MSTP114, MSTP113, MSTP112,
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MSTP111, MSTP110, MSTP103, MSTP102, MSTP220,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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/* MSTPCR0 */
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[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
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[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
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/* MSTPCR1 */
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[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
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[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
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[MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
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[MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
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[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
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[MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
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[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
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[MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
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/* MSTPCR2 */
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[MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]),
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CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]),
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CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]),
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CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]),
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CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]),
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CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]),
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CLKDEV_CON_ID("riic5", &mstp_clks[MSTP000]),
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CLKDEV_CON_ID("riic6", &mstp_clks[MSTP000]),
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CLKDEV_CON_ID("riic7", &mstp_clks[MSTP000]),
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CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP113]),
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CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP114]),
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CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP112]),
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CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP111]),
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CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP110]),
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CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]),
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CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
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CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
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CLKDEV_DEV_ID("rspi.2", &mstp_clks[MSTP127]),
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};
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int __init arch_clk_init(void)
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{
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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ret |= clk_register(clks[i]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
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&div4_table);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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return ret;
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}
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