422 lines
13 KiB
C
422 lines
13 KiB
C
/*
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* This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
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* driver for Linux.
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*
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* Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __T4VF_COMMON_H__
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#define __T4VF_COMMON_H__
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#include "../cxgb4/t4_hw.h"
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#include "../cxgb4/t4fw_api.h"
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#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
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#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
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#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
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/* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
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*
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* V = "4" for T4; "5" for T5, etc. or
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* = "a" for T4 FPGA; "b" for T4 FPGA, etc.
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* F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
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* PP = adapter product designation
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*/
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#define CHELSIO_T4 0x4
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#define CHELSIO_T5 0x5
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#define CHELSIO_T6 0x6
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enum chip_type {
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T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
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T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
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T4_FIRST_REV = T4_A1,
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T4_LAST_REV = T4_A2,
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T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
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T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
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T5_FIRST_REV = T5_A0,
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T5_LAST_REV = T5_A1,
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};
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/*
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* The "len16" field of a Firmware Command Structure ...
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*/
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#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
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/*
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* Per-VF statistics.
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*/
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struct t4vf_port_stats {
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/*
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* TX statistics.
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*/
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u64 tx_bcast_bytes; /* broadcast */
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u64 tx_bcast_frames;
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u64 tx_mcast_bytes; /* multicast */
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u64 tx_mcast_frames;
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u64 tx_ucast_bytes; /* unicast */
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u64 tx_ucast_frames;
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u64 tx_drop_frames; /* TX dropped frames */
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u64 tx_offload_bytes; /* offload */
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u64 tx_offload_frames;
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/*
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* RX statistics.
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*/
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u64 rx_bcast_bytes; /* broadcast */
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u64 rx_bcast_frames;
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u64 rx_mcast_bytes; /* multicast */
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u64 rx_mcast_frames;
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u64 rx_ucast_bytes;
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u64 rx_ucast_frames; /* unicast */
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u64 rx_err_frames; /* RX error frames */
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};
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/*
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* Per-"port" (Virtual Interface) link configuration ...
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*/
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typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
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typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
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enum fw_caps {
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FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
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FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
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FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
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};
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enum cc_pause {
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PAUSE_RX = 1 << 0,
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PAUSE_TX = 1 << 1,
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PAUSE_AUTONEG = 1 << 2
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};
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enum cc_fec {
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FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
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FEC_RS = 1 << 1, /* Reed-Solomon */
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FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
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};
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struct link_config {
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fw_port_cap32_t pcaps; /* link capabilities */
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fw_port_cap32_t acaps; /* advertised capabilities */
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fw_port_cap32_t lpacaps; /* peer advertised capabilities */
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fw_port_cap32_t speed_caps; /* speed(s) user has requested */
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u32 speed; /* actual link speed */
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enum cc_pause requested_fc; /* flow control user has requested */
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enum cc_pause fc; /* actual link flow control */
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enum cc_fec auto_fec; /* Forward Error Correction: */
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enum cc_fec requested_fec; /* "automatic" (IEEE 802.3), */
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enum cc_fec fec; /* requested, and actual in use */
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unsigned char autoneg; /* autonegotiating? */
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unsigned char link_ok; /* link up? */
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unsigned char link_down_rc; /* link down reason */
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};
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/* Return true if the Link Configuration supports "High Speeds" (those greater
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* than 1Gb/s).
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*/
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static inline bool is_x_10g_port(const struct link_config *lc)
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{
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fw_port_cap32_t speeds, high_speeds;
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speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
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high_speeds =
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speeds & ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
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return high_speeds != 0;
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}
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/*
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* General device parameters ...
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*/
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struct dev_params {
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u32 fwrev; /* firmware version */
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u32 tprev; /* TP Microcode Version */
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};
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/*
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* Scatter Gather Engine parameters. These are almost all determined by the
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* Physical Function Driver. We just need to grab them to see within which
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* environment we're playing ...
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*/
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struct sge_params {
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u32 sge_control; /* padding, boundaries, lengths, etc. */
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u32 sge_control2; /* T5: more of the same */
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u32 sge_host_page_size; /* PF0-7 page sizes */
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u32 sge_egress_queues_per_page; /* PF0-7 egress queues/page */
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u32 sge_ingress_queues_per_page;/* PF0-7 ingress queues/page */
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u32 sge_vf_hps; /* host page size for our vf */
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u32 sge_vf_eq_qpp; /* egress queues/page for our VF */
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u32 sge_vf_iq_qpp; /* ingress queues/page for our VF */
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u32 sge_fl_buffer_size[16]; /* free list buffer sizes */
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u32 sge_ingress_rx_threshold; /* RX counter interrupt threshold[4] */
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u32 sge_congestion_control; /* congestion thresholds, etc. */
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u32 sge_timer_value_0_and_1; /* interrupt coalescing timer values */
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u32 sge_timer_value_2_and_3;
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u32 sge_timer_value_4_and_5;
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};
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/*
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* Vital Product Data parameters.
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*/
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struct vpd_params {
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u32 cclk; /* Core Clock (KHz) */
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};
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/* Stores chip specific parameters */
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struct arch_specific_params {
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u32 sge_fl_db;
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u16 mps_tcam_size;
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};
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/*
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* Global Receive Side Scaling (RSS) parameters in host-native format.
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*/
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struct rss_params {
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unsigned int mode; /* RSS mode */
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union {
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struct {
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unsigned int synmapen:1; /* SYN Map Enable */
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unsigned int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
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unsigned int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
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unsigned int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
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unsigned int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
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unsigned int ofdmapen:1; /* Offload Map Enable */
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unsigned int tnlmapen:1; /* Tunnel Map Enable */
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unsigned int tnlalllookup:1; /* Tunnel All Lookup */
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unsigned int hashtoeplitz:1; /* use Toeplitz hash */
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} basicvirtual;
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} u;
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};
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/*
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* Virtual Interface RSS Configuration in host-native format.
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*/
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union rss_vi_config {
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struct {
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u16 defaultq; /* Ingress Queue ID for !tnlalllookup */
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unsigned int ip6fourtupen:1; /* hash 4-tuple IPv6 ingress packets */
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unsigned int ip6twotupen:1; /* hash 2-tuple IPv6 ingress packets */
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unsigned int ip4fourtupen:1; /* hash 4-tuple IPv4 ingress packets */
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unsigned int ip4twotupen:1; /* hash 2-tuple IPv4 ingress packets */
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int udpen; /* hash 4-tuple UDP ingress packets */
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} basicvirtual;
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};
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/*
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* Maximum resources provisioned for a PCI VF.
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*/
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struct vf_resources {
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unsigned int nvi; /* N virtual interfaces */
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unsigned int neq; /* N egress Qs */
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unsigned int nethctrl; /* N egress ETH or CTRL Qs */
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unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
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unsigned int niq; /* N ingress Qs */
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unsigned int tc; /* PCI-E traffic class */
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unsigned int pmask; /* port access rights mask */
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unsigned int nexactf; /* N exact MPS filters */
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unsigned int r_caps; /* read capabilities */
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unsigned int wx_caps; /* write/execute capabilities */
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};
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/*
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* Per-"adapter" (Virtual Function) parameters.
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*/
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struct adapter_params {
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struct dev_params dev; /* general device parameters */
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struct sge_params sge; /* Scatter Gather Engine */
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struct vpd_params vpd; /* Vital Product Data */
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struct rss_params rss; /* Receive Side Scaling */
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struct vf_resources vfres; /* Virtual Function Resource limits */
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struct arch_specific_params arch; /* chip specific params */
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enum chip_type chip; /* chip code */
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u8 nports; /* # of Ethernet "ports" */
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u8 fw_caps_support; /* 32-bit Port Capabilities */
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};
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/* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
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* The access and execute times are signed in order to accommodate negative
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* error returns.
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*/
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struct mbox_cmd {
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u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
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u64 timestamp; /* OS-dependent timestamp */
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u32 seqno; /* sequence number */
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s16 access; /* time (ms) to access mailbox */
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s16 execute; /* time (ms) to execute */
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};
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struct mbox_cmd_log {
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unsigned int size; /* number of entries in the log */
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unsigned int cursor; /* next position in the log to write */
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u32 seqno; /* next sequence number */
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/* variable length mailbox command log starts here */
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};
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/* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
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* return a pointer to the specified entry.
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*/
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static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
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unsigned int entry_idx)
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{
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return &((struct mbox_cmd *)&(log)[1])[entry_idx];
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}
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#include "adapter.h"
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#ifndef PCI_VENDOR_ID_CHELSIO
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# define PCI_VENDOR_ID_CHELSIO 0x1425
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#endif
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#define for_each_port(adapter, iter) \
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for (iter = 0; iter < (adapter)->params.nports; iter++)
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static inline unsigned int core_ticks_per_usec(const struct adapter *adapter)
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{
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return adapter->params.vpd.cclk / 1000;
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}
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static inline unsigned int us_to_core_ticks(const struct adapter *adapter,
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unsigned int us)
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{
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return (us * adapter->params.vpd.cclk) / 1000;
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}
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static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
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unsigned int ticks)
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{
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return (ticks * 1000) / adapter->params.vpd.cclk;
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}
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int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
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static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
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int size, void *rpl)
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{
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return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
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}
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static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
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int size, void *rpl)
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{
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return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
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}
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#define CHELSIO_PCI_ID_VER(dev_id) ((dev_id) >> 12)
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static inline int is_t4(enum chip_type chip)
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{
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return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
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}
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/**
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* hash_mac_addr - return the hash value of a MAC address
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* @addr: the 48-bit Ethernet MAC address
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*
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* Hashes a MAC address according to the hash function used by hardware
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* inexact (hash) address matching.
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*/
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static inline int hash_mac_addr(const u8 *addr)
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{
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u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
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u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
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a ^= b;
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a ^= (a >> 12);
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a ^= (a >> 6);
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return a & 0x3f;
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}
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int t4vf_wait_dev_ready(struct adapter *);
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int t4vf_port_init(struct adapter *, int);
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int t4vf_fw_reset(struct adapter *);
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int t4vf_set_params(struct adapter *, unsigned int, const u32 *, const u32 *);
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int t4vf_fl_pkt_align(struct adapter *adapter);
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enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
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int t4vf_bar2_sge_qregs(struct adapter *adapter,
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unsigned int qid,
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enum t4_bar2_qtype qtype,
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u64 *pbar2_qoffset,
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unsigned int *pbar2_qid);
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unsigned int t4vf_get_pf_from_vf(struct adapter *);
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int t4vf_get_sge_params(struct adapter *);
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int t4vf_get_vpd_params(struct adapter *);
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int t4vf_get_dev_params(struct adapter *);
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int t4vf_get_rss_glb_config(struct adapter *);
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int t4vf_get_vfres(struct adapter *);
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int t4vf_read_rss_vi_config(struct adapter *, unsigned int,
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union rss_vi_config *);
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int t4vf_write_rss_vi_config(struct adapter *, unsigned int,
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union rss_vi_config *);
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int t4vf_config_rss_range(struct adapter *, unsigned int, int, int,
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const u16 *, int);
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int t4vf_alloc_vi(struct adapter *, int);
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int t4vf_free_vi(struct adapter *, int);
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int t4vf_enable_vi(struct adapter *adapter, unsigned int viid, bool rx_en,
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bool tx_en);
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int t4vf_enable_pi(struct adapter *adapter, struct port_info *pi, bool rx_en,
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bool tx_en);
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int t4vf_identify_port(struct adapter *, unsigned int, unsigned int);
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int t4vf_set_rxmode(struct adapter *, unsigned int, int, int, int, int, int,
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bool);
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int t4vf_alloc_mac_filt(struct adapter *, unsigned int, bool, unsigned int,
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const u8 **, u16 *, u64 *, bool);
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int t4vf_free_mac_filt(struct adapter *, unsigned int, unsigned int naddr,
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const u8 **, bool);
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int t4vf_change_mac(struct adapter *, unsigned int, int, const u8 *, bool);
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int t4vf_set_addr_hash(struct adapter *, unsigned int, bool, u64, bool);
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int t4vf_get_port_stats(struct adapter *, int, struct t4vf_port_stats *);
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int t4vf_iq_free(struct adapter *, unsigned int, unsigned int, unsigned int,
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unsigned int);
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int t4vf_eth_eq_free(struct adapter *, unsigned int);
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int t4vf_update_port_info(struct port_info *pi);
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int t4vf_handle_fw_rpl(struct adapter *, const __be64 *);
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int t4vf_prep_adapter(struct adapter *);
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int t4vf_get_vf_mac_acl(struct adapter *adapter, unsigned int pf,
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unsigned int *naddr, u8 *addr);
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int t4vf_get_vf_vlan_acl(struct adapter *adapter);
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#endif /* __T4VF_COMMON_H__ */
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