511 lines
12 KiB
C
511 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <linux/if.h>
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#include <linux/list.h>
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#include <linux/if_ether.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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#include <linux/netlink.h>
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#include <linux/bitops.h>
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#include <net/genetlink.h>
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#include <linux/delay.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/lockdep.h>
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#include <linux/workqueue.h>
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#include <linux/of_device.h>
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#include "mt753x.h"
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#include "mt753x_swconfig.h"
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#include "mt753x_regs.h"
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#define MT753X_PORT_MIB_TXB_ID 18 /* TxByte */
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#define MT753X_PORT_MIB_RXB_ID 37 /* RxByte */
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#define MIB_DESC(_s, _o, _n) \
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{ \
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.size = (_s), \
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.offset = (_o), \
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.name = (_n), \
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}
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struct mt753x_mib_desc {
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unsigned int size;
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unsigned int offset;
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const char *name;
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};
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static const struct mt753x_mib_desc mt753x_mibs[] = {
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MIB_DESC(1, STATS_TDPC, "TxDrop"),
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MIB_DESC(1, STATS_TCRC, "TxCRC"),
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MIB_DESC(1, STATS_TUPC, "TxUni"),
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MIB_DESC(1, STATS_TMPC, "TxMulti"),
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MIB_DESC(1, STATS_TBPC, "TxBroad"),
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MIB_DESC(1, STATS_TCEC, "TxCollision"),
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MIB_DESC(1, STATS_TSCEC, "TxSingleCol"),
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MIB_DESC(1, STATS_TMCEC, "TxMultiCol"),
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MIB_DESC(1, STATS_TDEC, "TxDefer"),
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MIB_DESC(1, STATS_TLCEC, "TxLateCol"),
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MIB_DESC(1, STATS_TXCEC, "TxExcCol"),
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MIB_DESC(1, STATS_TPPC, "TxPause"),
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MIB_DESC(1, STATS_TL64PC, "Tx64Byte"),
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MIB_DESC(1, STATS_TL65PC, "Tx65Byte"),
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MIB_DESC(1, STATS_TL128PC, "Tx128Byte"),
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MIB_DESC(1, STATS_TL256PC, "Tx256Byte"),
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MIB_DESC(1, STATS_TL512PC, "Tx512Byte"),
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MIB_DESC(1, STATS_TL1024PC, "Tx1024Byte"),
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MIB_DESC(2, STATS_TOC, "TxByte"),
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MIB_DESC(1, STATS_RDPC, "RxDrop"),
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MIB_DESC(1, STATS_RFPC, "RxFiltered"),
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MIB_DESC(1, STATS_RUPC, "RxUni"),
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MIB_DESC(1, STATS_RMPC, "RxMulti"),
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MIB_DESC(1, STATS_RBPC, "RxBroad"),
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MIB_DESC(1, STATS_RAEPC, "RxAlignErr"),
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MIB_DESC(1, STATS_RCEPC, "RxCRC"),
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MIB_DESC(1, STATS_RUSPC, "RxUnderSize"),
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MIB_DESC(1, STATS_RFEPC, "RxFragment"),
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MIB_DESC(1, STATS_ROSPC, "RxOverSize"),
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MIB_DESC(1, STATS_RJEPC, "RxJabber"),
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MIB_DESC(1, STATS_RPPC, "RxPause"),
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MIB_DESC(1, STATS_RL64PC, "Rx64Byte"),
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MIB_DESC(1, STATS_RL65PC, "Rx65Byte"),
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MIB_DESC(1, STATS_RL128PC, "Rx128Byte"),
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MIB_DESC(1, STATS_RL256PC, "Rx256Byte"),
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MIB_DESC(1, STATS_RL512PC, "Rx512Byte"),
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MIB_DESC(1, STATS_RL1024PC, "Rx1024Byte"),
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MIB_DESC(2, STATS_ROC, "RxByte"),
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MIB_DESC(1, STATS_RDPC_CTRL, "RxCtrlDrop"),
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MIB_DESC(1, STATS_RDPC_ING, "RxIngDrop"),
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MIB_DESC(1, STATS_RDPC_ARL, "RxARLDrop")
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};
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enum {
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/* Global attributes. */
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MT753X_ATTR_ENABLE_VLAN,
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};
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static int mt753x_get_vlan_enable(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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val->value.i = gsw->global_vlan_enable;
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return 0;
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}
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static int mt753x_set_vlan_enable(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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gsw->global_vlan_enable = val->value.i != 0;
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return 0;
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}
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static int mt753x_get_port_pvid(struct switch_dev *dev, int port, int *val)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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if (port >= MT753X_NUM_PORTS)
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return -EINVAL;
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*val = mt753x_reg_read(gsw, PPBV1(port));
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*val &= GRP_PORT_VID_M;
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return 0;
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}
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static int mt753x_set_port_pvid(struct switch_dev *dev, int port, int pvid)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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if (port >= MT753X_NUM_PORTS)
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return -EINVAL;
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if (pvid < MT753X_MIN_VID || pvid > MT753X_MAX_VID)
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return -EINVAL;
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gsw->port_entries[port].pvid = pvid;
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return 0;
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}
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static int mt753x_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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u32 member;
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u32 etags;
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int i;
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val->len = 0;
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if (val->port_vlan < 0 || val->port_vlan >= MT753X_NUM_VLANS)
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return -EINVAL;
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mt753x_vlan_ctrl(gsw, VTCR_READ_VLAN_ENTRY, val->port_vlan);
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member = mt753x_reg_read(gsw, VAWD1);
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member &= PORT_MEM_M;
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member >>= PORT_MEM_S;
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etags = mt753x_reg_read(gsw, VAWD2);
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for (i = 0; i < MT753X_NUM_PORTS; i++) {
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struct switch_port *p;
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int etag;
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if (!(member & BIT(i)))
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continue;
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p = &val->value.ports[val->len++];
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p->id = i;
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etag = (etags >> PORT_ETAG_S(i)) & PORT_ETAG_M;
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if (etag == ETAG_CTRL_TAG)
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p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
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else if (etag != ETAG_CTRL_UNTAG)
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dev_info(gsw->dev,
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"vlan egress tag control neither untag nor tag.\n");
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}
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return 0;
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}
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static int mt753x_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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u8 member = 0;
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u8 etags = 0;
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int i;
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if (val->port_vlan < 0 || val->port_vlan >= MT753X_NUM_VLANS ||
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val->len > MT753X_NUM_PORTS)
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return -EINVAL;
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for (i = 0; i < val->len; i++) {
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struct switch_port *p = &val->value.ports[i];
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if (p->id >= MT753X_NUM_PORTS)
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return -EINVAL;
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member |= BIT(p->id);
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if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
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etags |= BIT(p->id);
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}
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gsw->vlan_entries[val->port_vlan].member = member;
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gsw->vlan_entries[val->port_vlan].etags = etags;
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return 0;
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}
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static int mt753x_set_vid(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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int vlan;
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u16 vid;
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vlan = val->port_vlan;
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vid = (u16)val->value.i;
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if (vlan < 0 || vlan >= MT753X_NUM_VLANS)
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return -EINVAL;
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if (vid < MT753X_MIN_VID || vid > MT753X_MAX_VID)
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return -EINVAL;
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gsw->vlan_entries[vlan].vid = vid;
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return 0;
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}
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static int mt753x_get_vid(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val)
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{
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val->value.i = val->port_vlan;
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return 0;
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}
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static int mt753x_get_port_link(struct switch_dev *dev, int port,
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struct switch_port_link *link)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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u32 speed, pmsr;
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if (port < 0 || port >= MT753X_NUM_PORTS)
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return -EINVAL;
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pmsr = mt753x_reg_read(gsw, PMSR(port));
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link->link = pmsr & MAC_LNK_STS;
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link->duplex = pmsr & MAC_DPX_STS;
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speed = (pmsr & MAC_SPD_STS_M) >> MAC_SPD_STS_S;
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switch (speed) {
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case MAC_SPD_10:
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link->speed = SWITCH_PORT_SPEED_10;
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break;
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case MAC_SPD_100:
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link->speed = SWITCH_PORT_SPEED_100;
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break;
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case MAC_SPD_1000:
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link->speed = SWITCH_PORT_SPEED_1000;
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break;
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case MAC_SPD_2500:
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/* TODO: swconfig has no support for 2500 now */
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link->speed = SWITCH_PORT_SPEED_UNKNOWN;
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break;
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}
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return 0;
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}
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static int mt753x_set_port_link(struct switch_dev *dev, int port,
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struct switch_port_link *link)
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{
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#ifndef MODULE
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if (port >= MT753X_NUM_PHYS)
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return -EINVAL;
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return switch_generic_set_link(dev, port, link);
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#else
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return -ENOTSUPP;
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#endif
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}
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static u64 get_mib_counter(struct gsw_mt753x *gsw, int i, int port)
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{
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unsigned int offset;
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u64 lo, hi, hi2;
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offset = mt753x_mibs[i].offset;
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if (mt753x_mibs[i].size == 1)
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return mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset));
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do {
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hi = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset + 4));
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lo = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset));
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hi2 = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset + 4));
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} while (hi2 != hi);
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return (hi << 32) | lo;
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}
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static int mt753x_get_port_mib(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val)
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{
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static char buf[4096];
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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int i, len = 0;
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if (val->port_vlan >= MT753X_NUM_PORTS)
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return -EINVAL;
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len += snprintf(buf + len, sizeof(buf) - len,
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"Port %d MIB counters\n", val->port_vlan);
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for (i = 0; i < ARRAY_SIZE(mt753x_mibs); ++i) {
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u64 counter;
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len += snprintf(buf + len, sizeof(buf) - len,
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"%-11s: ", mt753x_mibs[i].name);
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counter = get_mib_counter(gsw, i, val->port_vlan);
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len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
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counter);
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}
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val->value.s = buf;
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val->len = len;
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return 0;
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}
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static int mt753x_get_port_stats(struct switch_dev *dev, int port,
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struct switch_port_stats *stats)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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if (port < 0 || port >= MT753X_NUM_PORTS)
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return -EINVAL;
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stats->tx_bytes = get_mib_counter(gsw, MT753X_PORT_MIB_TXB_ID, port);
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stats->rx_bytes = get_mib_counter(gsw, MT753X_PORT_MIB_RXB_ID, port);
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return 0;
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}
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static void mt753x_port_isolation(struct gsw_mt753x *gsw)
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{
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int i;
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for (i = 0; i < MT753X_NUM_PORTS; i++)
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mt753x_reg_write(gsw, PCR(i),
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BIT(gsw->cpu_port) << PORT_MATRIX_S);
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mt753x_reg_write(gsw, PCR(gsw->cpu_port), PORT_MATRIX_M);
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for (i = 0; i < MT753X_NUM_PORTS; i++)
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mt753x_reg_write(gsw, PVC(i),
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(0x8100 << STAG_VPID_S) |
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(VA_TRANSPARENT_PORT << VLAN_ATTR_S));
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}
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static int mt753x_apply_config(struct switch_dev *dev)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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if (!gsw->global_vlan_enable) {
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mt753x_port_isolation(gsw);
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return 0;
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}
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mt753x_apply_vlan_config(gsw);
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return 0;
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}
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static int mt753x_reset_switch(struct switch_dev *dev)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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int i;
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memset(gsw->port_entries, 0, sizeof(gsw->port_entries));
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memset(gsw->vlan_entries, 0, sizeof(gsw->vlan_entries));
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/* set default vid of each vlan to the same number of vlan, so the vid
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* won't need be set explicitly.
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*/
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for (i = 0; i < MT753X_NUM_VLANS; i++)
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gsw->vlan_entries[i].vid = i;
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return 0;
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}
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static int mt753x_phy_read16(struct switch_dev *dev, int addr, u8 reg,
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u16 *value)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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*value = gsw->mii_read(gsw, addr, reg);
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return 0;
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}
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static int mt753x_phy_write16(struct switch_dev *dev, int addr, u8 reg,
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u16 value)
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{
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struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);
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gsw->mii_write(gsw, addr, reg, value);
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return 0;
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}
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static const struct switch_attr mt753x_global[] = {
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{
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.type = SWITCH_TYPE_INT,
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.name = "enable_vlan",
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.description = "VLAN mode (1:enabled)",
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.max = 1,
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.id = MT753X_ATTR_ENABLE_VLAN,
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.get = mt753x_get_vlan_enable,
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.set = mt753x_set_vlan_enable,
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}
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};
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static const struct switch_attr mt753x_port[] = {
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{
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.type = SWITCH_TYPE_STRING,
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.name = "mib",
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.description = "Get MIB counters for port",
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.get = mt753x_get_port_mib,
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.set = NULL,
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},
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};
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static const struct switch_attr mt753x_vlan[] = {
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{
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.type = SWITCH_TYPE_INT,
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.name = "vid",
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.description = "VLAN ID (0-4094)",
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.set = mt753x_set_vid,
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.get = mt753x_get_vid,
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.max = 4094,
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},
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};
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static const struct switch_dev_ops mt753x_swdev_ops = {
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.attr_global = {
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.attr = mt753x_global,
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.n_attr = ARRAY_SIZE(mt753x_global),
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},
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.attr_port = {
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.attr = mt753x_port,
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.n_attr = ARRAY_SIZE(mt753x_port),
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},
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.attr_vlan = {
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.attr = mt753x_vlan,
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.n_attr = ARRAY_SIZE(mt753x_vlan),
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},
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.get_vlan_ports = mt753x_get_vlan_ports,
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.set_vlan_ports = mt753x_set_vlan_ports,
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.get_port_pvid = mt753x_get_port_pvid,
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.set_port_pvid = mt753x_set_port_pvid,
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.get_port_link = mt753x_get_port_link,
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.set_port_link = mt753x_set_port_link,
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.get_port_stats = mt753x_get_port_stats,
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.apply_config = mt753x_apply_config,
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.reset_switch = mt753x_reset_switch,
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.phy_read16 = mt753x_phy_read16,
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.phy_write16 = mt753x_phy_write16,
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};
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int mt753x_swconfig_init(struct gsw_mt753x *gsw)
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{
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struct device_node *np = gsw->dev->of_node;
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struct switch_dev *swdev;
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int ret;
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if (of_property_read_u32(np, "mediatek,cpuport", &gsw->cpu_port))
|
|
gsw->cpu_port = MT753X_DFL_CPU_PORT;
|
|
|
|
swdev = &gsw->swdev;
|
|
|
|
swdev->name = gsw->name;
|
|
swdev->alias = gsw->name;
|
|
swdev->cpu_port = gsw->cpu_port;
|
|
swdev->ports = MT753X_NUM_PORTS;
|
|
swdev->vlans = MT753X_NUM_VLANS;
|
|
swdev->ops = &mt753x_swdev_ops;
|
|
|
|
ret = register_switch(swdev, NULL);
|
|
if (ret) {
|
|
dev_notice(gsw->dev, "Failed to register switch %s\n",
|
|
swdev->name);
|
|
return ret;
|
|
}
|
|
|
|
mt753x_apply_config(swdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mt753x_swconfig_destroy(struct gsw_mt753x *gsw)
|
|
{
|
|
unregister_switch(&gsw->swdev);
|
|
}
|