6db4831e98
Android 14
184 lines
4.1 KiB
C
184 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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*/
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#include "mt753x.h"
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#include "mt753x_regs.h"
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struct mt753x_mapping mt753x_def_mapping[] = {
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{
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.name = "llllw",
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.pvids = { 1, 1, 1, 1, 2, 2, 1 },
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.members = { 0, 0x4f, 0x30 },
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.etags = { 0, 0, 0 },
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.vids = { 0, 1, 2 },
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}, {
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.name = "wllll",
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.pvids = { 2, 1, 1, 1, 1, 2, 1 },
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.members = { 0, 0x5e, 0x21 },
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.etags = { 0, 0, 0 },
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.vids = { 0, 1, 2 },
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}, {
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.name = "lwlll",
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.pvids = { 1, 2, 1, 1, 1, 2, 1 },
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.members = { 0, 0x5d, 0x22 },
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.etags = { 0, 0, 0 },
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.vids = { 0, 1, 2 },
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},
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};
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void mt753x_vlan_ctrl(struct gsw_mt753x *gsw, u32 cmd, u32 val)
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{
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int i;
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mt753x_reg_write(gsw, VTCR,
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VTCR_BUSY | ((cmd << VTCR_FUNC_S) & VTCR_FUNC_M) |
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(val & VTCR_VID_M));
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for (i = 0; i < 300; i++) {
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u32 val = mt753x_reg_read(gsw, VTCR);
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if ((val & VTCR_BUSY) == 0)
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break;
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usleep_range(1000, 1100);
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}
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if (i == 300)
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dev_info(gsw->dev, "vtcr timeout\n");
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}
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static void mt753x_write_vlan_entry(struct gsw_mt753x *gsw, int vlan, u16 vid,
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u8 ports, u8 etags)
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{
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int port;
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u32 val;
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/* vlan port membership */
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if (ports)
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mt753x_reg_write(gsw, VAWD1,
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IVL_MAC | VTAG_EN | VENTRY_VALID |
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((ports << PORT_MEM_S) & PORT_MEM_M));
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else
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mt753x_reg_write(gsw, VAWD1, 0);
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/* egress mode */
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val = 0;
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for (port = 0; port < MT753X_NUM_PORTS; port++) {
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if (etags & BIT(port))
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val |= ETAG_CTRL_TAG << PORT_ETAG_S(port);
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else
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val |= ETAG_CTRL_UNTAG << PORT_ETAG_S(port);
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}
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mt753x_reg_write(gsw, VAWD2, val);
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/* write to vlan table */
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mt753x_vlan_ctrl(gsw, VTCR_WRITE_VLAN_ENTRY, vid);
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}
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void mt753x_apply_vlan_config(struct gsw_mt753x *gsw)
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{
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int i, j;
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u8 tag_ports;
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u8 untag_ports;
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/* set all ports as security mode */
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for (i = 0; i < MT753X_NUM_PORTS; i++)
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mt753x_reg_write(gsw, PCR(i),
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PORT_MATRIX_M | SECURITY_MODE);
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/* check if a port is used in tag/untag vlan egress mode */
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tag_ports = 0;
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untag_ports = 0;
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for (i = 0; i < MT753X_NUM_VLANS; i++) {
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u8 member = gsw->vlan_entries[i].member;
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u8 etags = gsw->vlan_entries[i].etags;
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if (!member)
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continue;
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for (j = 0; j < MT753X_NUM_PORTS; j++) {
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if (!(member & BIT(j)))
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continue;
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if (etags & BIT(j))
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tag_ports |= 1u << j;
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else
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untag_ports |= 1u << j;
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}
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}
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/* set all untag-only ports as transparent and the rest as user port */
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for (i = 0; i < MT753X_NUM_PORTS; i++) {
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u32 pvc_mode = 0x8100 << STAG_VPID_S;
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if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
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pvc_mode = (0x8100 << STAG_VPID_S) |
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(VA_TRANSPARENT_PORT << VLAN_ATTR_S);
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mt753x_reg_write(gsw, PVC(i), pvc_mode);
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}
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/* first clear the switch vlan table */
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for (i = 0; i < MT753X_NUM_VLANS; i++)
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mt753x_write_vlan_entry(gsw, i, i, 0, 0);
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/* now program only vlans with members to avoid
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* clobbering remapped entries in later iterations
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*/
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for (i = 0; i < MT753X_NUM_VLANS; i++) {
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u16 vid = gsw->vlan_entries[i].vid;
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u8 member = gsw->vlan_entries[i].member;
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u8 etags = gsw->vlan_entries[i].etags;
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if (member)
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mt753x_write_vlan_entry(gsw, i, vid, member, etags);
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}
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/* Port Default PVID */
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for (i = 0; i < MT753X_NUM_PORTS; i++) {
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int vlan = gsw->port_entries[i].pvid;
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u16 pvid = 0;
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u32 val;
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if (vlan < MT753X_NUM_VLANS && gsw->vlan_entries[vlan].member)
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pvid = gsw->vlan_entries[vlan].vid;
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val = mt753x_reg_read(gsw, PPBV1(i));
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val &= ~GRP_PORT_VID_M;
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val |= pvid;
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mt753x_reg_write(gsw, PPBV1(i), val);
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}
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}
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struct mt753x_mapping *mt753x_find_mapping(struct device_node *np)
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{
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const char *map;
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int i;
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if (of_property_read_string(np, "mediatek,portmap", &map))
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return NULL;
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for (i = 0; i < ARRAY_SIZE(mt753x_def_mapping); i++)
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if (!strcmp(map, mt753x_def_mapping[i].name))
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return &mt753x_def_mapping[i];
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return NULL;
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}
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void mt753x_apply_mapping(struct gsw_mt753x *gsw, struct mt753x_mapping *map)
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{
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int i = 0;
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for (i = 0; i < MT753X_NUM_PORTS; i++)
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gsw->port_entries[i].pvid = map->pvids[i];
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for (i = 0; i < MT753X_NUM_VLANS; i++) {
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gsw->vlan_entries[i].member = map->members[i];
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gsw->vlan_entries[i].etags = map->etags[i];
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gsw->vlan_entries[i].vid = map->vids[i];
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}
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}
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