1557 lines
38 KiB
Plaintext
1557 lines
38 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* SAMSUNG EXYNOS5420 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
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* EXYNOS5420 based board files can include this file and provide
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* values for board specfic bindings.
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*/
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#include "exynos54xx.dtsi"
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#include <dt-bindings/clock/exynos5420.h>
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#include <dt-bindings/clock/exynos-audss-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "samsung,exynos5420", "samsung,exynos5";
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aliases {
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mshc0 = &mmc_0;
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mshc1 = &mmc_1;
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mshc2 = &mmc_2;
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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pinctrl4 = &pinctrl_4;
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i2c8 = &hsi2c_8;
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i2c9 = &hsi2c_9;
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i2c10 = &hsi2c_10;
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gsc0 = &gsc_0;
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gsc1 = &gsc_1;
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spi0 = &spi_0;
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spi1 = &spi_1;
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spi2 = &spi_2;
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};
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/*
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* The 'cpus' node is not present here but instead it is provided
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* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
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*/
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soc: soc {
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cluster_a15_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1250000>;
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clock-latency-ns = <140000>;
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};
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opp-1700000000 {
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opp-hz = /bits/ 64 <1700000000>;
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opp-microvolt = <1212500>;
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clock-latency-ns = <140000>;
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};
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opp-1600000000 {
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opp-hz = /bits/ 64 <1600000000>;
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opp-microvolt = <1175000>;
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clock-latency-ns = <140000>;
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};
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opp-1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <1137500>;
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clock-latency-ns = <140000>;
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};
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opp-1400000000 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-microvolt = <1112500>;
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clock-latency-ns = <140000>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1062500>;
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clock-latency-ns = <140000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1037500>;
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clock-latency-ns = <140000>;
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};
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opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <1012500>;
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clock-latency-ns = <140000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = < 987500>;
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clock-latency-ns = <140000>;
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};
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = < 962500>;
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clock-latency-ns = <140000>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = < 937500>;
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clock-latency-ns = <140000>;
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};
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opp-700000000 {
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opp-hz = /bits/ 64 <700000000>;
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opp-microvolt = < 912500>;
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clock-latency-ns = <140000>;
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};
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};
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cluster_a7_opp_table: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1275000>;
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clock-latency-ns = <140000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1212500>;
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clock-latency-ns = <140000>;
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};
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opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <1162500>;
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clock-latency-ns = <140000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1112500>;
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clock-latency-ns = <140000>;
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};
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <1062500>;
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clock-latency-ns = <140000>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1025000>;
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clock-latency-ns = <140000>;
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};
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opp-700000000 {
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opp-hz = /bits/ 64 <700000000>;
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opp-microvolt = <975000>;
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clock-latency-ns = <140000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <937500>;
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clock-latency-ns = <140000>;
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};
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};
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cci: cci@10d20000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10d20000 0x1000>;
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ranges = <0x0 0x10d20000 0x6000>;
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cci_control0: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control1: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5420-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5420-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
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<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
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power-domains = <&mau_pd>;
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};
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mfc: codec@11000000 {
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compatible = "samsung,mfc-v7";
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reg = <0x11000000 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_MFC>;
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clock-names = "mfc";
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power-domains = <&mfc_pd>;
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iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
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iommu-names = "left", "right";
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};
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mmc_0: mmc@12200000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12200000 0x2000>;
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clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_1: mmc@12210000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12210000 0x2000>;
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clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_2: mmc@12220000 {
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compatible = "samsung,exynos5420-dw-mshc";
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12220000 0x1000>;
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clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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nocp_mem0_0: nocp@10ca1000 {
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compatible = "samsung,exynos5420-nocp";
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reg = <0x10CA1000 0x200>;
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status = "disabled";
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};
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nocp_mem0_1: nocp@10ca1400 {
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compatible = "samsung,exynos5420-nocp";
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reg = <0x10CA1400 0x200>;
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status = "disabled";
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};
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nocp_mem1_0: nocp@10ca1800 {
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compatible = "samsung,exynos5420-nocp";
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reg = <0x10CA1800 0x200>;
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status = "disabled";
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};
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nocp_mem1_1: nocp@10ca1c00 {
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compatible = "samsung,exynos5420-nocp";
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reg = <0x10CA1C00 0x200>;
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status = "disabled";
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};
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nocp_g3d_0: nocp@11a51000 {
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compatible = "samsung,exynos5420-nocp";
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reg = <0x11A51000 0x200>;
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status = "disabled";
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};
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nocp_g3d_1: nocp@11a51400 {
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compatible = "samsung,exynos5420-nocp";
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reg = <0x11A51400 0x200>;
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status = "disabled";
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};
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gsc_pd: power-domain@10044000 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044000 0x20>;
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#power-domain-cells = <0>;
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label = "GSC";
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};
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isp_pd: power-domain@10044020 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044020 0x20>;
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#power-domain-cells = <0>;
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label = "ISP";
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};
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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#power-domain-cells = <0>;
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label = "MFC";
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};
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msc_pd: power-domain@10044120 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044120 0x20>;
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#power-domain-cells = <0>;
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label = "MSC";
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};
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disp_pd: power-domain@100440c0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440C0 0x20>;
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#power-domain-cells = <0>;
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label = "DISP";
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};
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mau_pd: power-domain@100440e0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440E0 0x20>;
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#power-domain-cells = <0>;
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label = "MAU";
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};
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pinctrl_0: pinctrl@13400000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13400000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl_1: pinctrl@13410000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13410000 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_2: pinctrl@14000000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14000000 0x1000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_3: pinctrl@14010000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14010000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_4: pinctrl@3860000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&mau_pd>;
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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adma: adma@3880000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x03880000 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_audss EXYNOS_ADMA>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <6>;
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#dma-requests = <16>;
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power-domains = <&mau_pd>;
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};
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pdma0: pdma@121a0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121A0000 0x1000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_PDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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pdma1: pdma@121b0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121B0000 0x1000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_PDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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mdma0: mdma@10800000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x10800000 0x1000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_MDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <1>;
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};
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mdma1: mdma@11c10000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x11C10000 0x1000>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_MDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <1>;
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/*
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* MDMA1 can support both secure and non-secure
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* AXI transactions. When this is enabled in
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* the kernel for boards that run in secure
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* mode, we are getting imprecise external
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* aborts causing the kernel to oops.
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*/
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status = "disabled";
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};
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};
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i2s0: i2s@3830000 {
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compatible = "samsung,exynos5420-i2s";
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reg = <0x03830000 0x100>;
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dmas = <&adma 0
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&adma 2
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&adma 1>;
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dma-names = "tx", "rx", "tx-sec";
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clocks = <&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_SCLK_I2S>;
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clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk0";
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#sound-dai-cells = <1>;
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samsung,idma-addr = <0x03000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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power-domains = <&mau_pd>;
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status = "disabled";
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};
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i2s1: i2s@12d60000 {
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compatible = "samsung,exynos5420-i2s";
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reg = <0x12D60000 0x100>;
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dmas = <&pdma1 12
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&pdma1 11>;
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dma-names = "tx", "rx";
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clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
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clock-names = "iis", "i2s_opclk0";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk1";
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#sound-dai-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_bus>;
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status = "disabled";
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};
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i2s2: i2s@12d70000 {
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compatible = "samsung,exynos5420-i2s";
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reg = <0x12D70000 0x100>;
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dmas = <&pdma0 12
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&pdma0 11>;
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dma-names = "tx", "rx";
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clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
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clock-names = "iis", "i2s_opclk0";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk2";
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#sound-dai-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s2_bus>;
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status = "disabled";
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};
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spi_0: spi@12d20000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d20000 0x100>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma0 5
|
|
&pdma0 4>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_bus>;
|
|
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_1: spi@12d30000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d30000 0x100>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma1 5
|
|
&pdma1 4>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_2: spi@12d40000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d40000 0x100>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&pdma0 7
|
|
&pdma0 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
dp_phy: dp-video-phy {
|
|
compatible = "samsung,exynos5420-dp-video-phy";
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
mipi_phy: mipi-video-phy {
|
|
compatible = "samsung,s5pv210-mipi-video-phy";
|
|
syscon = <&pmu_system_controller>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
dsi@14500000 {
|
|
compatible = "samsung,exynos5410-mipi-dsi";
|
|
reg = <0x14500000 0x10000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&mipi_phy 1>;
|
|
phy-names = "dsim";
|
|
clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
|
|
clock-names = "bus_clk", "pll_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@12d10000 {
|
|
compatible = "samsung,exynos-adc-v2";
|
|
reg = <0x12D10000 0x100>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_TSADC>;
|
|
clock-names = "adc";
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_8: i2c@12e00000 {
|
|
compatible = "samsung,exynos5250-hsi2c";
|
|
reg = <0x12E00000 0x1000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8_hs_bus>;
|
|
clocks = <&clock CLK_USI4>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_9: i2c@12e10000 {
|
|
compatible = "samsung,exynos5250-hsi2c";
|
|
reg = <0x12E10000 0x1000>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c9_hs_bus>;
|
|
clocks = <&clock CLK_USI5>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_10: i2c@12e20000 {
|
|
compatible = "samsung,exynos5250-hsi2c";
|
|
reg = <0x12E20000 0x1000>;
|
|
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c10_hs_bus>;
|
|
clocks = <&clock CLK_USI6>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi: hdmi@14530000 {
|
|
compatible = "samsung,exynos5420-hdmi";
|
|
reg = <0x14530000 0x70000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
|
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
|
<&clock CLK_MOUT_HDMI>;
|
|
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
|
"sclk_hdmiphy", "mout_hdmi";
|
|
phy = <&hdmiphy>;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
power-domains = <&disp_pd>;
|
|
#sound-dai-cells = <0>;
|
|
};
|
|
|
|
hdmiphy: hdmiphy@145d0000 {
|
|
reg = <0x145D0000 0x20>;
|
|
};
|
|
|
|
hdmicec: cec@101b0000 {
|
|
compatible = "samsung,s5p-cec";
|
|
reg = <0x101B0000 0x200>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_HDMI_CEC>;
|
|
clock-names = "hdmicec";
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
hdmi-phandle = <&hdmi>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hdmi_cec>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mixer: mixer@14450000 {
|
|
compatible = "samsung,exynos5420-mixer";
|
|
reg = <0x14450000 0x10000>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
|
<&clock CLK_SCLK_HDMI>;
|
|
clock-names = "mixer", "hdmi", "sclk_hdmi";
|
|
power-domains = <&disp_pd>;
|
|
iommus = <&sysmmu_tv>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rotator: rotator@11c00000 {
|
|
compatible = "samsung,exynos5250-rotator";
|
|
reg = <0x11C00000 0x64>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_ROTATOR>;
|
|
clock-names = "rotator";
|
|
iommus = <&sysmmu_rotator>;
|
|
};
|
|
|
|
gsc_0: video-scaler@13e00000 {
|
|
compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
|
|
reg = <0x13e00000 0x1000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_GSCL0>;
|
|
clock-names = "gscl";
|
|
power-domains = <&gsc_pd>;
|
|
iommus = <&sysmmu_gscl0>;
|
|
};
|
|
|
|
gsc_1: video-scaler@13e10000 {
|
|
compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
|
|
reg = <0x13e10000 0x1000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_GSCL1>;
|
|
clock-names = "gscl";
|
|
power-domains = <&gsc_pd>;
|
|
iommus = <&sysmmu_gscl1>;
|
|
};
|
|
|
|
scaler_0: scaler@12800000 {
|
|
compatible = "samsung,exynos5420-scaler";
|
|
reg = <0x12800000 0x1294>;
|
|
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_MSCL0>;
|
|
clock-names = "mscl";
|
|
power-domains = <&msc_pd>;
|
|
iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
|
|
};
|
|
|
|
scaler_1: scaler@12810000 {
|
|
compatible = "samsung,exynos5420-scaler";
|
|
reg = <0x12810000 0x1294>;
|
|
interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_MSCL1>;
|
|
clock-names = "mscl";
|
|
power-domains = <&msc_pd>;
|
|
iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
|
|
};
|
|
|
|
scaler_2: scaler@12820000 {
|
|
compatible = "samsung,exynos5420-scaler";
|
|
reg = <0x12820000 0x1294>;
|
|
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_MSCL2>;
|
|
clock-names = "mscl";
|
|
power-domains = <&msc_pd>;
|
|
iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
|
|
};
|
|
|
|
jpeg_0: jpeg@11f50000 {
|
|
compatible = "samsung,exynos5420-jpeg";
|
|
reg = <0x11F50000 0x1000>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "jpeg";
|
|
clocks = <&clock CLK_JPEG>;
|
|
iommus = <&sysmmu_jpeg0>;
|
|
};
|
|
|
|
jpeg_1: jpeg@11f60000 {
|
|
compatible = "samsung,exynos5420-jpeg";
|
|
reg = <0x11F60000 0x1000>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "jpeg";
|
|
clocks = <&clock CLK_JPEG2>;
|
|
iommus = <&sysmmu_jpeg1>;
|
|
};
|
|
|
|
pmu_system_controller: system-controller@10040000 {
|
|
compatible = "samsung,exynos5420-pmu", "syscon";
|
|
reg = <0x10040000 0x5000>;
|
|
clock-names = "clkout16";
|
|
clocks = <&clock CLK_FIN_PLL>;
|
|
#clock-cells = <1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
tmu_cpu0: tmu@10060000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10060000 0x100>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif";
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
tmu_cpu1: tmu@10064000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10064000 0x100>;
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif";
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
tmu_cpu2: tmu@10068000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
tmu_cpu3: tmu@1006c000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
tmu_gpu: tmu@100a0000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
|
|
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
sysmmu_g2dr: sysmmu@10a60000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x10A60000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <24 5>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_g2dw: sysmmu@10a70000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x10A70000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <22 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_tv: sysmmu@14650000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x14650000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <7 4>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
|
|
power-domains = <&disp_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_gscl0: sysmmu@13e80000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x13E80000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
|
|
power-domains = <&gsc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_gscl1: sysmmu@13e90000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x13E90000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
|
|
power-domains = <&gsc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler0r: sysmmu@12880000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x12880000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <22 4>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
|
|
power-domains = <&msc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler1r: sysmmu@12890000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x12890000 0x1000>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
|
|
power-domains = <&msc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler2r: sysmmu@128a0000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x128A0000 0x1000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
|
|
power-domains = <&msc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler0w: sysmmu@128c0000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x128C0000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <27 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
|
|
power-domains = <&msc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler1w: sysmmu@128d0000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x128D0000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <22 6>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
|
|
power-domains = <&msc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler2w: sysmmu@128e0000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x128E0000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <19 6>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
|
|
power-domains = <&msc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_rotator: sysmmu@11d40000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11D40000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <4 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_jpeg0: sysmmu@11f10000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11F10000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <4 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_jpeg1: sysmmu@11f20000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11F20000 0x1000>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_mfc_l: sysmmu@11200000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11200000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <6 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
|
|
power-domains = <&mfc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_mfc_r: sysmmu@11210000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11210000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <8 5>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
|
|
power-domains = <&mfc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimd1_0: sysmmu@14640000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x14640000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <3 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
|
|
power-domains = <&disp_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimd1_1: sysmmu@14680000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x14680000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <3 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
|
|
power-domains = <&disp_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
bus_wcore: bus_wcore {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_wcore_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_noc: bus_noc {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_noc_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_fsys_apb: bus_fsys_apb {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_fsys_apb_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_fsys: bus_fsys {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_fsys_apb_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_fsys2: bus_fsys2 {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_fsys2_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_mfc: bus_mfc {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK333>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_mfc_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_gen: bus_gen {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK266>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_gen_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_peri: bus_peri {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK66>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_peri_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_g2d: bus_g2d {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_g2d_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_g2d_acp: bus_g2d_acp {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_g2d_acp_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_jpeg: bus_jpeg {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_jpeg_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_jpeg_apb: bus_jpeg_apb {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK166>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_disp1_fimd: bus_disp1_fimd {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_disp1: bus_disp1 {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_disp1_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_gscl_scaler: bus_gscl_scaler {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_gscl_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_mscl: bus_mscl {
|
|
compatible = "samsung,exynos-bus";
|
|
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&bus_mscl_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bus_wcore_opp_table: opp_table2 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <84000000>;
|
|
opp-microvolt = <925000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <111000000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <222000000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <333000000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <400000000>;
|
|
opp-microvolt = <987500>;
|
|
};
|
|
};
|
|
|
|
bus_noc_opp_table: opp_table3 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <67000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <75000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <86000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
};
|
|
};
|
|
|
|
bus_fsys_apb_opp_table: opp_table4 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
};
|
|
|
|
bus_fsys2_opp_table: opp_table5 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <75000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <150000000>;
|
|
};
|
|
};
|
|
|
|
bus_mfc_opp_table: opp_table6 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <96000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <111000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <167000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <222000000>;
|
|
};
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <333000000>;
|
|
};
|
|
};
|
|
|
|
bus_gen_opp_table: opp_table7 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <89000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <133000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <178000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <267000000>;
|
|
};
|
|
};
|
|
|
|
bus_peri_opp_table: opp_table8 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <67000000>;
|
|
};
|
|
};
|
|
|
|
bus_g2d_opp_table: opp_table9 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <84000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <167000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <222000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
};
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <333000000>;
|
|
};
|
|
};
|
|
|
|
bus_g2d_acp_opp_table: opp_table10 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <67000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <133000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <178000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <267000000>;
|
|
};
|
|
};
|
|
|
|
bus_jpeg_opp_table: opp_table11 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <75000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <150000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
};
|
|
};
|
|
|
|
bus_jpeg_apb_opp_table: opp_table12 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <84000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <111000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <134000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <167000000>;
|
|
};
|
|
};
|
|
|
|
bus_disp1_fimd_opp_table: opp_table13 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <120000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
};
|
|
|
|
bus_disp1_opp_table: opp_table14 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <120000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
};
|
|
};
|
|
|
|
bus_gscl_opp_table: opp_table15 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <150000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
};
|
|
};
|
|
|
|
bus_mscl_opp_table: opp_table16 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <84000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <167000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <222000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <333000000>;
|
|
};
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <400000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu0_thermal: cpu0-thermal {
|
|
thermal-sensors = <&tmu_cpu0>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
cpu1_thermal: cpu1-thermal {
|
|
thermal-sensors = <&tmu_cpu1>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
cpu2_thermal: cpu2-thermal {
|
|
thermal-sensors = <&tmu_cpu2>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
cpu3_thermal: cpu3-thermal {
|
|
thermal-sensors = <&tmu_cpu3>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
gpu_thermal: gpu-thermal {
|
|
thermal-sensors = <&tmu_gpu>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
};
|
|
};
|
|
|
|
&dp {
|
|
clocks = <&clock CLK_DP1>;
|
|
clock-names = "dp";
|
|
phys = <&dp_phy>;
|
|
phy-names = "dp";
|
|
power-domains = <&disp_pd>;
|
|
};
|
|
|
|
&fimd {
|
|
compatible = "samsung,exynos5420-fimd";
|
|
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
|
|
clock-names = "sclk_fimd", "fimd";
|
|
power-domains = <&disp_pd>;
|
|
iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
|
|
iommu-names = "m0", "m1";
|
|
};
|
|
|
|
&g2d {
|
|
iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
|
|
clocks = <&clock CLK_G2D>;
|
|
clock-names = "fimg2d";
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c_0 {
|
|
clocks = <&clock CLK_I2C0>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_bus>;
|
|
};
|
|
|
|
&i2c_1 {
|
|
clocks = <&clock CLK_I2C1>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_bus>;
|
|
};
|
|
|
|
&i2c_2 {
|
|
clocks = <&clock CLK_I2C2>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_bus>;
|
|
};
|
|
|
|
&i2c_3 {
|
|
clocks = <&clock CLK_I2C3>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
};
|
|
|
|
&hsi2c_4 {
|
|
clocks = <&clock CLK_USI0>;
|
|
clock-names = "hsi2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_hs_bus>;
|
|
};
|
|
|
|
&hsi2c_5 {
|
|
clocks = <&clock CLK_USI1>;
|
|
clock-names = "hsi2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_hs_bus>;
|
|
};
|
|
|
|
&hsi2c_6 {
|
|
clocks = <&clock CLK_USI2>;
|
|
clock-names = "hsi2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_hs_bus>;
|
|
};
|
|
|
|
&hsi2c_7 {
|
|
clocks = <&clock CLK_USI3>;
|
|
clock-names = "hsi2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7_hs_bus>;
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|
};
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|
|
|
&mct {
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|
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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|
clock-names = "fin_pll", "mct";
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|
};
|
|
|
|
&prng {
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|
clocks = <&clock CLK_SSS>;
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|
clock-names = "secss";
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|
};
|
|
|
|
&pwm {
|
|
clocks = <&clock CLK_PWM>;
|
|
clock-names = "timers";
|
|
};
|
|
|
|
&rtc {
|
|
clocks = <&clock CLK_RTC>;
|
|
clock-names = "rtc";
|
|
interrupt-parent = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
&serial_0 {
|
|
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
dmas = <&pdma0 13>, <&pdma0 14>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
&serial_1 {
|
|
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
dmas = <&pdma1 15>, <&pdma1 16>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
&serial_2 {
|
|
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
dmas = <&pdma0 15>, <&pdma0 16>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
&serial_3 {
|
|
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
dmas = <&pdma1 17>, <&pdma1 18>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
&sss {
|
|
clocks = <&clock CLK_SSS>;
|
|
clock-names = "secss";
|
|
};
|
|
|
|
&trng {
|
|
clocks = <&clock CLK_SSS>;
|
|
clock-names = "secss";
|
|
};
|
|
|
|
&usbdrd3_0 {
|
|
clocks = <&clock CLK_USBD300>;
|
|
clock-names = "usbdrd30";
|
|
};
|
|
|
|
&usbdrd_phy0 {
|
|
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
|
|
clock-names = "phy", "ref";
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
};
|
|
|
|
&usbdrd3_1 {
|
|
clocks = <&clock CLK_USBD301>;
|
|
clock-names = "usbdrd30";
|
|
};
|
|
|
|
&usbdrd_dwc3_1 {
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&usbdrd_phy1 {
|
|
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
|
|
clock-names = "phy", "ref";
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
};
|
|
|
|
&usbhost1 {
|
|
clocks = <&clock CLK_USBH20>;
|
|
clock-names = "usbhost";
|
|
};
|
|
|
|
&usbhost2 {
|
|
clocks = <&clock CLK_USBH20>;
|
|
clock-names = "usbhost";
|
|
};
|
|
|
|
&usb2_phy {
|
|
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
|
|
clock-names = "phy", "ref";
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
samsung,pmureg-phandle = <&pmu_system_controller>;
|
|
};
|
|
|
|
&watchdog {
|
|
clocks = <&clock CLK_WDT>;
|
|
clock-names = "watchdog";
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
};
|
|
|
|
#include "exynos5420-pinctrl.dtsi"
|
|
#include "exynos-syscon-restart.dtsi"
|