789 lines
19 KiB
Plaintext
789 lines
19 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
#include "tegra30.dtsi"
|
|
|
|
/*
|
|
* Toradex Apalis T30 Module Device Tree
|
|
* Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
|
|
* 2GB: V1.0B, V1.0C, V1.0E, V1.1A
|
|
*/
|
|
/ {
|
|
model = "Toradex Apalis T30";
|
|
compatible = "toradex,apalis_t30", "nvidia,tegra30";
|
|
|
|
memory@80000000 {
|
|
reg = <0x80000000 0x40000000>;
|
|
};
|
|
|
|
pcie@3000 {
|
|
avdd-pexa-supply = <&vdd2_reg>;
|
|
vdd-pexa-supply = <&vdd2_reg>;
|
|
avdd-pexb-supply = <&vdd2_reg>;
|
|
vdd-pexb-supply = <&vdd2_reg>;
|
|
avdd-pex-pll-supply = <&vdd2_reg>;
|
|
avdd-plle-supply = <&ldo6_reg>;
|
|
vddio-pex-ctl-supply = <&sys_3v3_reg>;
|
|
hvdd-pex-supply = <&sys_3v3_reg>;
|
|
|
|
pci@1,0 {
|
|
nvidia,num-lanes = <4>;
|
|
};
|
|
|
|
pci@2,0 {
|
|
nvidia,num-lanes = <1>;
|
|
};
|
|
|
|
pci@3,0 {
|
|
nvidia,num-lanes = <1>;
|
|
};
|
|
};
|
|
|
|
host1x@50000000 {
|
|
hdmi@54280000 {
|
|
vdd-supply = <&avdd_hdmi_3v3_reg>;
|
|
pll-supply = <&avdd_hdmi_pll_1v8_reg>;
|
|
|
|
nvidia,hpd-gpio =
|
|
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
|
|
nvidia,ddc-i2c-bus = <&hdmiddc>;
|
|
};
|
|
};
|
|
|
|
pinmux@70000868 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&state_default>;
|
|
|
|
state_default: pinmux {
|
|
/* Analogue Audio (On-module) */
|
|
clk1_out_pw4 {
|
|
nvidia,pins = "clk1_out_pw4";
|
|
nvidia,function = "extperiph1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap3_fs_pp0 {
|
|
nvidia,pins = "dap3_fs_pp0",
|
|
"dap3_sclk_pp3",
|
|
"dap3_din_pp1",
|
|
"dap3_dout_pp2";
|
|
nvidia,function = "i2s2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis BKL1_ON */
|
|
pv2 {
|
|
nvidia,pins = "pv2";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis BKL1_PWM */
|
|
uart3_rts_n_pc0 {
|
|
nvidia,pins = "uart3_rts_n_pc0";
|
|
nvidia,function = "pwm0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
/* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
|
|
uart3_cts_n_pa1 {
|
|
nvidia,pins = "uart3_cts_n_pa1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis CAN1 on SPI6 */
|
|
spi2_cs0_n_px3 {
|
|
nvidia,pins = "spi2_cs0_n_px3",
|
|
"spi2_miso_px1",
|
|
"spi2_mosi_px0",
|
|
"spi2_sck_px2";
|
|
nvidia,function = "spi6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
/* CAN_INT1 */
|
|
spi2_cs1_n_pw2 {
|
|
nvidia,pins = "spi2_cs1_n_pw2";
|
|
nvidia,function = "spi3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis CAN2 on SPI4 */
|
|
gmi_a16_pj7 {
|
|
nvidia,pins = "gmi_a16_pj7",
|
|
"gmi_a17_pb0",
|
|
"gmi_a18_pb1",
|
|
"gmi_a19_pk7";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
/* CAN_INT2 */
|
|
spi2_cs2_n_pw3 {
|
|
nvidia,pins = "spi2_cs2_n_pw3";
|
|
nvidia,function = "spi3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis Digital Audio */
|
|
clk1_req_pee2 {
|
|
nvidia,pins = "clk1_req_pee2";
|
|
nvidia,function = "hda";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
clk2_out_pw5 {
|
|
nvidia,pins = "clk2_out_pw5";
|
|
nvidia,function = "extperiph2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap1_fs_pn0 {
|
|
nvidia,pins = "dap1_fs_pn0",
|
|
"dap1_din_pn1",
|
|
"dap1_dout_pn2",
|
|
"dap1_sclk_pn3";
|
|
nvidia,function = "hda";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis I2C3 */
|
|
cam_i2c_scl_pbb1 {
|
|
nvidia,pins = "cam_i2c_scl_pbb1",
|
|
"cam_i2c_sda_pbb2";
|
|
nvidia,function = "i2c3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis MMC1 */
|
|
sdmmc3_clk_pa6 {
|
|
nvidia,pins = "sdmmc3_clk_pa6";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_dat0_pb7 {
|
|
nvidia,pins = "sdmmc3_cmd_pa7",
|
|
"sdmmc3_dat0_pb7",
|
|
"sdmmc3_dat1_pb6",
|
|
"sdmmc3_dat2_pb5",
|
|
"sdmmc3_dat3_pb4",
|
|
"sdmmc3_dat4_pd1",
|
|
"sdmmc3_dat5_pd0",
|
|
"sdmmc3_dat6_pd3",
|
|
"sdmmc3_dat7_pd4";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
/* Apalis MMC1_CD# */
|
|
pv3 {
|
|
nvidia,pins = "pv3";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis PWM1 */
|
|
pu6 {
|
|
nvidia,pins = "pu6";
|
|
nvidia,function = "pwm3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis PWM2 */
|
|
pu5 {
|
|
nvidia,pins = "pu5";
|
|
nvidia,function = "pwm2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis PWM3 */
|
|
pu4 {
|
|
nvidia,pins = "pu4";
|
|
nvidia,function = "pwm1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis PWM4 */
|
|
pu3 {
|
|
nvidia,pins = "pu3";
|
|
nvidia,function = "pwm0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis RESET_MOCI# */
|
|
gmi_rst_n_pi4 {
|
|
nvidia,pins = "gmi_rst_n_pi4";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis SD1 */
|
|
sdmmc1_clk_pz0 {
|
|
nvidia,pins = "sdmmc1_clk_pz0";
|
|
nvidia,function = "sdmmc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_cmd_pz1 {
|
|
nvidia,pins = "sdmmc1_cmd_pz1",
|
|
"sdmmc1_dat0_py7",
|
|
"sdmmc1_dat1_py6",
|
|
"sdmmc1_dat2_py5",
|
|
"sdmmc1_dat3_py4";
|
|
nvidia,function = "sdmmc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
/* Apalis SD1_CD# */
|
|
clk2_req_pcc5 {
|
|
nvidia,pins = "clk2_req_pcc5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis SPI1 */
|
|
spi1_sck_px5 {
|
|
nvidia,pins = "spi1_sck_px5",
|
|
"spi1_mosi_px4",
|
|
"spi1_miso_px7",
|
|
"spi1_cs0_n_px6";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis SPI2 */
|
|
lcd_sck_pz4 {
|
|
nvidia,pins = "lcd_sck_pz4",
|
|
"lcd_sdout_pn5",
|
|
"lcd_sdin_pz2",
|
|
"lcd_cs0_n_pn4";
|
|
nvidia,function = "spi5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis UART1 */
|
|
ulpi_data0 {
|
|
nvidia,pins = "ulpi_data0_po1",
|
|
"ulpi_data1_po2",
|
|
"ulpi_data2_po3",
|
|
"ulpi_data3_po4",
|
|
"ulpi_data4_po5",
|
|
"ulpi_data5_po6",
|
|
"ulpi_data6_po7",
|
|
"ulpi_data7_po0";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis UART2 */
|
|
ulpi_clk_py0 {
|
|
nvidia,pins = "ulpi_clk_py0",
|
|
"ulpi_dir_py1",
|
|
"ulpi_nxt_py2",
|
|
"ulpi_stp_py3";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis UART3 */
|
|
uart2_rxd_pc3 {
|
|
nvidia,pins = "uart2_rxd_pc3",
|
|
"uart2_txd_pc2";
|
|
nvidia,function = "uartb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis UART4 */
|
|
uart3_rxd_pw7 {
|
|
nvidia,pins = "uart3_rxd_pw7",
|
|
"uart3_txd_pw6";
|
|
nvidia,function = "uartc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis USBO1_EN */
|
|
gen2_i2c_scl_pt5 {
|
|
nvidia,pins = "gen2_i2c_scl_pt5";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Apalis USBO1_OC# */
|
|
gen2_i2c_sda_pt6 {
|
|
nvidia,pins = "gen2_i2c_sda_pt6";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* Apalis WAKE1_MICO */
|
|
pv1 {
|
|
nvidia,pins = "pv1";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* eMMC (On-module) */
|
|
sdmmc4_clk_pcc4 {
|
|
nvidia,pins = "sdmmc4_clk_pcc4",
|
|
"sdmmc4_rst_n_pcc3";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc4_dat0_paa0 {
|
|
nvidia,pins = "sdmmc4_dat0_paa0",
|
|
"sdmmc4_dat1_paa1",
|
|
"sdmmc4_dat2_paa2",
|
|
"sdmmc4_dat3_paa3",
|
|
"sdmmc4_dat4_paa4",
|
|
"sdmmc4_dat5_paa5",
|
|
"sdmmc4_dat6_paa6",
|
|
"sdmmc4_dat7_paa7";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* LVDS Transceiver Configuration */
|
|
pbb0 {
|
|
nvidia,pins = "pbb0",
|
|
"pbb7",
|
|
"pcc1",
|
|
"pcc2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pbb3 {
|
|
nvidia,pins = "pbb3",
|
|
"pbb4",
|
|
"pbb5",
|
|
"pbb6";
|
|
nvidia,function = "displayb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
|
|
/* Power I2C (On-module) */
|
|
pwr_i2c_scl_pz6 {
|
|
nvidia,pins = "pwr_i2c_scl_pz6",
|
|
"pwr_i2c_sda_pz7";
|
|
nvidia,function = "i2cpwr";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/*
|
|
* THERMD_ALERT#, unlatched I2C address pin of LM95245
|
|
* temperature sensor therefore requires disabling for
|
|
* now
|
|
*/
|
|
lcd_dc1_pd2 {
|
|
nvidia,pins = "lcd_dc1_pd2";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
|
|
/* TOUCH_PEN_INT# */
|
|
pv0 {
|
|
nvidia,pins = "pv0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmiddc: i2c@7000c700 {
|
|
clock-frequency = <10000>;
|
|
};
|
|
|
|
/*
|
|
* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
|
|
* touch screen controller
|
|
*/
|
|
i2c@7000d000 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
|
|
/* SGTL5000 audio codec */
|
|
sgtl5000: codec@a {
|
|
compatible = "fsl,sgtl5000";
|
|
reg = <0x0a>;
|
|
VDDA-supply = <&sys_3v3_reg>;
|
|
VDDIO-supply = <&sys_3v3_reg>;
|
|
clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
|
|
};
|
|
|
|
pmic: tps65911@2d {
|
|
compatible = "ti,tps65911";
|
|
reg = <0x2d>;
|
|
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
|
|
ti,system-power-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
|
|
vcc1-supply = <&sys_3v3_reg>;
|
|
vcc2-supply = <&sys_3v3_reg>;
|
|
vcc3-supply = <&vio_reg>;
|
|
vcc4-supply = <&sys_3v3_reg>;
|
|
vcc5-supply = <&sys_3v3_reg>;
|
|
vcc6-supply = <&vio_reg>;
|
|
vcc7-supply = <&charge_pump_5v0_reg>;
|
|
vccio-supply = <&sys_3v3_reg>;
|
|
|
|
regulators {
|
|
/* SW1: +V1.35_VDDIO_DDR */
|
|
vdd1_reg: vdd1 {
|
|
regulator-name = "vddio_ddr_1v35";
|
|
regulator-min-microvolt = <1350000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* SW2: +V1.05 */
|
|
vdd2_reg: vdd2 {
|
|
regulator-name =
|
|
"vdd_pexa,vdd_pexb,vdd_sata";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
};
|
|
|
|
/* SW CTRL: +V1.0_VDD_CPU */
|
|
vddctrl_reg: vddctrl {
|
|
regulator-name = "vdd_cpu,vdd_sys";
|
|
regulator-min-microvolt = <1150000>;
|
|
regulator-max-microvolt = <1150000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* SWIO: +V1.8 */
|
|
vio_reg: vio {
|
|
regulator-name = "vdd_1v8_gen";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* LDO1: unused */
|
|
|
|
/*
|
|
* EN_+V3.3 switching via FET:
|
|
* +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
|
|
* see also v3_3 fixed supply
|
|
*/
|
|
ldo2_reg: ldo2 {
|
|
regulator-name = "en_3v3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* +V1.2_CSI */
|
|
ldo3_reg: ldo3 {
|
|
regulator-name =
|
|
"avdd_dsi_csi,pwrdet_mipi";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
};
|
|
|
|
/* +V1.2_VDD_RTC */
|
|
ldo4_reg: ldo4 {
|
|
regulator-name = "vdd_rtc";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/*
|
|
* +V2.8_AVDD_VDAC:
|
|
* only required for analog RGB
|
|
*/
|
|
ldo5_reg: ldo5 {
|
|
regulator-name = "avdd_vdac";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/*
|
|
* +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
|
|
* but LDO6 can't set voltage in 50mV
|
|
* granularity
|
|
*/
|
|
ldo6_reg: ldo6 {
|
|
regulator-name = "avdd_plle";
|
|
regulator-min-microvolt = <1100000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
};
|
|
|
|
/* +V1.2_AVDD_PLL */
|
|
ldo7_reg: ldo7 {
|
|
regulator-name = "avdd_pll";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* +V1.0_VDD_DDR_HS */
|
|
ldo8_reg: ldo8 {
|
|
regulator-name = "vdd_ddr_hs";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* STMPE811 touch screen controller */
|
|
stmpe811@41 {
|
|
compatible = "st,stmpe811";
|
|
reg = <0x41>;
|
|
interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupt-controller;
|
|
id = <0>;
|
|
blocks = <0x5>;
|
|
irq-trigger = <0x1>;
|
|
|
|
stmpe_touchscreen {
|
|
compatible = "st,stmpe-ts";
|
|
/* 3.25 MHz ADC clock speed */
|
|
st,adc-freq = <1>;
|
|
/* 8 sample average control */
|
|
st,ave-ctrl = <3>;
|
|
/* 7 length fractional part in z */
|
|
st,fraction-z = <7>;
|
|
/*
|
|
* 50 mA typical 80 mA max touchscreen drivers
|
|
* current limit value
|
|
*/
|
|
st,i-drive = <1>;
|
|
/* 12-bit ADC */
|
|
st,mod-12b = <1>;
|
|
/* internal ADC reference */
|
|
st,ref-sel = <0>;
|
|
/* ADC converstion time: 80 clocks */
|
|
st,sample-time = <4>;
|
|
/* 1 ms panel driver settling time */
|
|
st,settling = <3>;
|
|
/* 5 ms touch detect interrupt delay */
|
|
st,touch-det-delay = <5>;
|
|
};
|
|
};
|
|
|
|
/*
|
|
* LM95245 temperature sensor
|
|
* Note: OVERT_N directly connected to PMIC PWRDN
|
|
*/
|
|
temp-sensor@4c {
|
|
compatible = "national,lm95245";
|
|
reg = <0x4c>;
|
|
};
|
|
|
|
/* SW: +V1.2_VDD_CORE */
|
|
tps62362@60 {
|
|
compatible = "ti,tps62362";
|
|
reg = <0x60>;
|
|
|
|
regulator-name = "tps62362-vout";
|
|
regulator-min-microvolt = <900000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
ti,vsel0-state-low;
|
|
/* VSEL1: EN_CORE_DVFS_N low for DVFS */
|
|
ti,vsel1-state-low;
|
|
};
|
|
};
|
|
|
|
/* SPI4: CAN2 */
|
|
spi@7000da00 {
|
|
status = "okay";
|
|
spi-max-frequency = <10000000>;
|
|
|
|
can@1 {
|
|
compatible = "microchip,mcp2515";
|
|
reg = <1>;
|
|
clocks = <&clk16m>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
|
|
spi-max-frequency = <10000000>;
|
|
};
|
|
};
|
|
|
|
/* SPI6: CAN1 */
|
|
spi@7000de00 {
|
|
status = "okay";
|
|
spi-max-frequency = <10000000>;
|
|
|
|
can@0 {
|
|
compatible = "microchip,mcp2515";
|
|
reg = <0>;
|
|
clocks = <&clk16m>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
|
|
spi-max-frequency = <10000000>;
|
|
};
|
|
};
|
|
|
|
pmc@7000e400 {
|
|
nvidia,invert-interrupt;
|
|
nvidia,suspend-mode = <1>;
|
|
nvidia,cpu-pwr-good-time = <5000>;
|
|
nvidia,cpu-pwr-off-time = <5000>;
|
|
nvidia,core-pwr-good-time = <3845 3845>;
|
|
nvidia,core-pwr-off-time = <0>;
|
|
nvidia,core-power-req-active-high;
|
|
nvidia,sys-clock-req-active-high;
|
|
};
|
|
|
|
ahub@70080000 {
|
|
i2s@70080500 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
/* eMMC */
|
|
sdhci@78000600 {
|
|
status = "okay";
|
|
bus-width = <8>;
|
|
non-removable;
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clk32k_in: clk@0 {
|
|
compatible = "fixed-clock";
|
|
reg = <0>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
clk16m: clk@1 {
|
|
compatible = "fixed-clock";
|
|
reg = <1>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <16000000>;
|
|
clock-output-names = "clk16m";
|
|
};
|
|
};
|
|
|
|
regulators {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
avdd_hdmi_pll_1v8_reg: regulator@100 {
|
|
compatible = "regulator-fixed";
|
|
reg = <100>;
|
|
regulator-name = "+V1.8_AVDD_HDMI_PLL";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
enable-active-high;
|
|
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
|
|
vin-supply = <&vio_reg>;
|
|
};
|
|
|
|
sys_3v3_reg: regulator@101 {
|
|
compatible = "regulator-fixed";
|
|
reg = <101>;
|
|
regulator-name = "3v3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
avdd_hdmi_3v3_reg: regulator@102 {
|
|
compatible = "regulator-fixed";
|
|
reg = <102>;
|
|
regulator-name = "+V3.3_AVDD_HDMI";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
enable-active-high;
|
|
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
|
|
vin-supply = <&sys_3v3_reg>;
|
|
};
|
|
|
|
charge_pump_5v0_reg: regulator@103 {
|
|
compatible = "regulator-fixed";
|
|
reg = <103>;
|
|
regulator-name = "5v0";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
|
|
sound {
|
|
compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
|
|
"nvidia,tegra-audio-sgtl5000";
|
|
nvidia,model = "Toradex Apalis T30";
|
|
nvidia,audio-routing =
|
|
"Headphone Jack", "HP_OUT",
|
|
"LINE_IN", "Line In Jack",
|
|
"MIC_IN", "Mic Jack";
|
|
nvidia,i2s-controller = <&tegra_i2s2>;
|
|
nvidia,audio-codec = <&sgtl5000>;
|
|
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
|
|
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
|
|
<&tegra_car TEGRA30_CLK_EXTERN1>;
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
|
};
|
|
};
|