166 lines
5 KiB
C
166 lines
5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/************************************************************************
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* Include file for TRIZEPS4 SoM and ConXS eval-board
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* Copyright (c) Jürgen Schindele
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* 2006
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************************************************************************/
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/*
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* Includes/Defines
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*/
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#ifndef _TRIPEPS4_H_
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#define _TRIPEPS4_H_
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#include "irqs.h" /* PXA_GPIO_TO_IRQ */
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/* physical memory regions */
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#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
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#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */
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#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
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#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
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#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
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/* Logic on ConXS-board CSFR register*/
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#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS)
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/* Logic on ConXS-board BOCR register*/
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#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000)
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/* Logic on ConXS-board IRCR register*/
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#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000)
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/* Logic on ConXS-board UPSR register*/
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#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000)
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/* Logic on ConXS-board DICR register*/
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#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000)
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/* virtual memory regions */
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#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
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#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */
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#define TRIZEPS4_CFSR_VIRT 0xF0100000
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#define TRIZEPS4_BOCR_VIRT 0xF0200000
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#define TRIZEPS4_DICR_VIRT 0xF0300000
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#define TRIZEPS4_IRCR_VIRT 0xF0400000
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#define TRIZEPS4_UPSR_VIRT 0xF0500000
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/* size of flash */
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#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
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/* Ethernet Controller Davicom DM9000 */
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#define GPIO_DM9000 101
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#define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000)
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/* UCB1400 audio / TS-controller */
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#define GPIO_UCB1400 1
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#define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400)
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/* PCMCIA socket Compact Flash */
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#define GPIO_PCD 11 /* PCMCIA Card Detect */
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#define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD)
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#define GPIO_PRDY 13 /* READY / nINT */
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#define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY)
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/* MMC socket */
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#define GPIO_MMC_DET 12
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#define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET)
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/* DOC NAND chip */
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#define GPIO_DOC_LOCK 94
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#define GPIO_DOC_IRQ 93
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#define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ)
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/* SPI interface */
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#define GPIO_SPI 53
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#define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI)
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/* LEDS using tx2 / rx2 */
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#define GPIO_SYS_BUSY_LED 46
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#define GPIO_HEARTBEAT_LED 47
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/* Off-module PIC on ConXS board */
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#define GPIO_PIC 0
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#define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC)
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#ifdef CONFIG_MACH_TRIZEPS_CONXS
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/* for CONXS base board define these registers */
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#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
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#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
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#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
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#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
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#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
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#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
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#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
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#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
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#ifndef __ASSEMBLY__
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static inline unsigned short CFSR_readw(void)
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{
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/* [Compact Flash Status Register] is read only */
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return *((unsigned short *)CFSR_P2V(0x0C000000));
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}
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static inline void BCR_writew(unsigned short value)
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{
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/* [Board Control Regsiter] is write only */
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*((unsigned short *)BCR_P2V(0x0E000000)) = value;
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}
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static inline void DCR_writew(unsigned short value)
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{
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/* [Display Control Register] is write only */
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*((unsigned short *)DCR_P2V(0x0E000000)) = value;
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}
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static inline void IRCR_writew(unsigned short value)
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{
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/* [InfraRed data Control Register] is write only */
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*((unsigned short *)IRCR_P2V(0x0E000000)) = value;
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}
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#else
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#define ConXS_CFSR CFSR_P2V(0x0C000000)
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#define ConXS_BCR BCR_P2V(0x0E000000)
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#define ConXS_DCR DCR_P2V(0x0F800000)
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#define ConXS_IRCR IRCR_P2V(0x0F800000)
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#endif
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#else
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/* for whatever baseboard define function registers */
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static inline unsigned short CFSR_readw(void)
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{
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return 0;
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}
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static inline void BCR_writew(unsigned short value)
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{
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;
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}
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static inline void DCR_writew(unsigned short value)
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{
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;
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}
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static inline void IRCR_writew(unsigned short value)
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{
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;
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}
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#endif /* CONFIG_MACH_TRIZEPS_CONXS */
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#define ConXS_CFSR_BVD_MASK 0x0003
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#define ConXS_CFSR_BVD1 (1 << 0)
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#define ConXS_CFSR_BVD2 (1 << 1)
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#define ConXS_CFSR_VS_MASK 0x000C
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#define ConXS_CFSR_VS1 (1 << 2)
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#define ConXS_CFSR_VS2 (1 << 3)
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#define ConXS_CFSR_VS_5V (0x3 << 2)
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#define ConXS_CFSR_VS_3V3 0x0
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#define ConXS_BCR_S0_POW_EN0 (1 << 0)
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#define ConXS_BCR_S0_POW_EN1 (1 << 1)
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#define ConXS_BCR_L_DISP (1 << 4)
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#define ConXS_BCR_CF_BUF_EN (1 << 5)
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#define ConXS_BCR_CF_RESET (1 << 7)
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#define ConXS_BCR_S0_VCC_3V3 0x1
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#define ConXS_BCR_S0_VCC_5V0 0x2
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#define ConXS_BCR_S0_VPP_12V 0x4
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#define ConXS_BCR_S0_VPP_3V3 0x8
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#define ConXS_IRCR_MODE (1 << 0)
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#define ConXS_IRCR_SD (1 << 1)
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#endif /* _TRIPEPS4_H_ */
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