30 lines
1.2 KiB
C
30 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017-2018 SiFive
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*/
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/*
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* There is explicitly no include guard here because this file is expected to
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* be included multiple times in order to define the syscall macros via
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* __SYSCALL.
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*/
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/*
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* Allows the instruction cache to be flushed from userspace. Despite RISC-V
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* having a direct 'fence.i' instruction available to userspace (which we
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* can't trap!), that's not actually viable when running on Linux because the
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* kernel might schedule a process on another hart. There is no way for
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* userspace to handle this without invoking the kernel (as it doesn't know the
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* thread->hart mappings), so we've defined a RISC-V specific system call to
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* flush the instruction cache.
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*
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* __NR_riscv_flush_icache is defined to flush the instruction cache over an
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* address range, with the flush applying to either all threads or just the
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* caller. We don't currently do anything with the address range, that's just
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* in there for forwards compatibility.
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*/
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#ifndef __NR_riscv_flush_icache
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#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
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#endif
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__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
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