164 lines
4 KiB
C
164 lines
4 KiB
C
/*
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* SMP initialisation and IPI support
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* Based on arch/arm64/kernel/smp.c
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/sched.h>
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#include <asm/sbi.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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/* A collection of single bit ipi messages. */
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static struct {
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unsigned long bits ____cacheline_aligned;
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} ipi_data[NR_CPUS] __cacheline_aligned;
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enum ipi_message_type {
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IPI_RESCHEDULE,
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IPI_CALL_FUNC,
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IPI_MAX
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};
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/* Unsupported */
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int setup_profiling_timer(unsigned int multiplier)
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{
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return -EINVAL;
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}
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void riscv_software_interrupt(void)
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{
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unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits;
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/* Clear pending IPI */
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csr_clear(sip, SIE_SSIE);
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while (true) {
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unsigned long ops;
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/* Order bit clearing and data access. */
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mb();
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ops = xchg(pending_ipis, 0);
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if (ops == 0)
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return;
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if (ops & (1 << IPI_RESCHEDULE))
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scheduler_ipi();
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if (ops & (1 << IPI_CALL_FUNC))
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generic_smp_call_function_interrupt();
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BUG_ON((ops >> IPI_MAX) != 0);
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/* Order data access and bit testing. */
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mb();
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}
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}
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static void
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send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation)
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{
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int i;
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mb();
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for_each_cpu(i, to_whom)
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set_bit(operation, &ipi_data[i].bits);
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mb();
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sbi_send_ipi(cpumask_bits(to_whom));
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}
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void arch_send_call_function_ipi_mask(struct cpumask *mask)
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{
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send_ipi_message(mask, IPI_CALL_FUNC);
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}
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void arch_send_call_function_single_ipi(int cpu)
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{
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send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
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}
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static void ipi_stop(void *unused)
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{
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while (1)
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wait_for_interrupt();
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}
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void smp_send_stop(void)
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{
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on_each_cpu(ipi_stop, NULL, 1);
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}
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void smp_send_reschedule(int cpu)
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{
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send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
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}
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/*
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* Performs an icache flush for the given MM context. RISC-V has no direct
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* mechanism for instruction cache shoot downs, so instead we send an IPI that
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* informs the remote harts they need to flush their local instruction caches.
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* To avoid pathologically slow behavior in a common case (a bunch of
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* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
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* IPIs for harts that are not currently executing a MM context and instead
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* schedule a deferred local instruction cache flush to be performed before
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* execution resumes on each hart.
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*/
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void flush_icache_mm(struct mm_struct *mm, bool local)
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{
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unsigned int cpu;
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cpumask_t others, *mask;
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preempt_disable();
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_flush_icache_all();
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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local |= cpumask_empty(&others);
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if (mm != current->active_mm || !local)
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sbi_remote_fence_i(others.bits);
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else {
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/*
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* It's assumed that at least one strongly ordered operation is
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* performed on this hart between setting a hart's cpumask bit
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* and scheduling this MM context on that hart. Sending an SBI
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* remote message will do this, but in the case where no
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* messages are sent we still need to order this hart's writes
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* with flush_icache_deferred().
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*/
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smp_mb();
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}
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preempt_enable();
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}
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