651 lines
16 KiB
C
651 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas System Solutions Asia Pte. Ltd - Migo-R
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*
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* Copyright (C) 2008 Magnus Damm
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*/
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#include <linux/clkdev.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/input.h>
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#include <linux/input/sh_keysc.h>
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#include <linux/memblock.h>
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#include <linux/mmc/host.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mfd/tmio.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/i2c.h>
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#include <linux/regulator/fixed.h>
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#include <linux/regulator/machine.h>
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#include <linux/smc91x.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/gpio/machine.h>
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#include <linux/videodev2.h>
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#include <linux/sh_intc.h>
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#include <video/sh_mobile_lcdc.h>
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#include <media/drv-intf/renesas-ceu.h>
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#include <media/i2c/ov772x.h>
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#include <media/i2c/tw9910.h>
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#include <asm/clock.h>
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#include <asm/machvec.h>
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#include <asm/io.h>
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#include <asm/suspend.h>
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#include <mach/migor.h>
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#include <cpu/sh7722.h>
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/* Address IRQ Size Bus Description
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* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
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* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
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* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
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* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
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* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
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*/
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#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
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static phys_addr_t ceu_dma_membase;
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static struct smc91x_platdata smc91x_info = {
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.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
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};
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static struct resource smc91x_eth_resources[] = {
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[0] = {
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.name = "SMC91C111" ,
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.start = 0x10000300,
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.end = 0x1000030f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x600), /* IRQ0 */
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
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},
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};
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static struct platform_device smc91x_eth_device = {
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.name = "smc91x",
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.num_resources = ARRAY_SIZE(smc91x_eth_resources),
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.resource = smc91x_eth_resources,
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.dev = {
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.platform_data = &smc91x_info,
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},
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};
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static struct sh_keysc_info sh_keysc_info = {
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.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
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.scan_timing = 3,
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.delay = 5,
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.keycodes = {
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0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
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0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
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0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
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0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
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0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
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},
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};
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static struct resource sh_keysc_resources[] = {
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[0] = {
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.start = 0x044b0000,
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.end = 0x044b000f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0xbe0),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device sh_keysc_device = {
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.name = "sh_keysc",
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.id = 0, /* "keysc0" clock */
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.num_resources = ARRAY_SIZE(sh_keysc_resources),
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.resource = sh_keysc_resources,
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.dev = {
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.platform_data = &sh_keysc_info,
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},
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};
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static struct mtd_partition migor_nor_flash_partitions[] =
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{
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{
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.name = "uboot",
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.offset = 0,
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.size = (1 * 1024 * 1024),
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.mask_flags = MTD_WRITEABLE, /* Read-only */
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},
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{
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.name = "rootfs",
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.offset = MTDPART_OFS_APPEND,
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.size = (15 * 1024 * 1024),
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},
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{
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.name = "other",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct physmap_flash_data migor_nor_flash_data = {
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.width = 2,
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.parts = migor_nor_flash_partitions,
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.nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
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};
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static struct resource migor_nor_flash_resources[] = {
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[0] = {
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.name = "NOR Flash",
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.start = 0x00000000,
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.end = 0x03ffffff,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct platform_device migor_nor_flash_device = {
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.name = "physmap-flash",
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.resource = migor_nor_flash_resources,
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.num_resources = ARRAY_SIZE(migor_nor_flash_resources),
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.dev = {
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.platform_data = &migor_nor_flash_data,
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},
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};
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static struct mtd_partition migor_nand_flash_partitions[] = {
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{
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.name = "nanddata1",
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.offset = 0x0,
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.size = 512 * 1024 * 1024,
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},
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{
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.name = "nanddata2",
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.offset = MTDPART_OFS_APPEND,
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.size = 512 * 1024 * 1024,
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},
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};
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static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, chip->IO_ADDR_W + 0x00400000);
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else if (ctrl & NAND_ALE)
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writeb(cmd, chip->IO_ADDR_W + 0x00800000);
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else
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writeb(cmd, chip->IO_ADDR_W);
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}
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static int migor_nand_flash_ready(struct mtd_info *mtd)
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{
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return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
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}
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static struct platform_nand_data migor_nand_flash_data = {
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.chip = {
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.nr_chips = 1,
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.partitions = migor_nand_flash_partitions,
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.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
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.chip_delay = 20,
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},
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.ctrl = {
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.dev_ready = migor_nand_flash_ready,
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.cmd_ctrl = migor_nand_flash_cmd_ctl,
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},
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};
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static struct resource migor_nand_flash_resources[] = {
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[0] = {
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.name = "NAND Flash",
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.start = 0x18000000,
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.end = 0x18ffffff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device migor_nand_flash_device = {
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.name = "gen_nand",
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.resource = migor_nand_flash_resources,
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.num_resources = ARRAY_SIZE(migor_nand_flash_resources),
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.dev = {
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.platform_data = &migor_nand_flash_data,
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}
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};
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static const struct fb_videomode migor_lcd_modes[] = {
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{
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#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
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.name = "LB070WV1",
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.xres = 800,
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.yres = 480,
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.left_margin = 64,
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.right_margin = 16,
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.hsync_len = 120,
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.sync = 0,
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#elif defined(CONFIG_SH_MIGOR_QVGA)
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.name = "PH240320T",
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.xres = 320,
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.yres = 240,
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.left_margin = 0,
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.right_margin = 16,
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.hsync_len = 8,
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.sync = FB_SYNC_HOR_HIGH_ACT,
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#endif
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.upper_margin = 1,
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.lower_margin = 17,
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.vsync_len = 2,
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},
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};
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static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
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#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
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.clock_source = LCDC_CLK_BUS,
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.ch[0] = {
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.chan = LCDC_CHAN_MAINLCD,
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.fourcc = V4L2_PIX_FMT_RGB565,
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.interface_type = RGB16,
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.clock_divider = 2,
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.lcd_modes = migor_lcd_modes,
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.num_modes = ARRAY_SIZE(migor_lcd_modes),
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.panel_cfg = { /* 7.0 inch */
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.width = 152,
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.height = 91,
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},
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}
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#elif defined(CONFIG_SH_MIGOR_QVGA)
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.clock_source = LCDC_CLK_PERIPHERAL,
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.ch[0] = {
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.chan = LCDC_CHAN_MAINLCD,
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.fourcc = V4L2_PIX_FMT_RGB565,
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.interface_type = SYS16A,
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.clock_divider = 10,
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.lcd_modes = migor_lcd_modes,
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.num_modes = ARRAY_SIZE(migor_lcd_modes),
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.panel_cfg = {
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.width = 49, /* 2.4 inch */
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.height = 37,
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.setup_sys = migor_lcd_qvga_setup,
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},
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.sys_bus_cfg = {
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.ldmt2r = 0x06000a09,
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.ldmt3r = 0x180e3418,
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/* set 1s delay to encourage fsync() */
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.deferred_io_msec = 1000,
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},
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}
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#endif
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};
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static struct resource migor_lcdc_resources[] = {
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[0] = {
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.name = "LCDC",
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.start = 0xfe940000, /* P4-only space */
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.end = 0xfe942fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x580),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device migor_lcdc_device = {
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.name = "sh_mobile_lcdc_fb",
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.num_resources = ARRAY_SIZE(migor_lcdc_resources),
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.resource = migor_lcdc_resources,
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.dev = {
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.platform_data = &sh_mobile_lcdc_info,
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},
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};
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static struct ceu_platform_data ceu_pdata = {
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.num_subdevs = 2,
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.subdevs = {
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{ /* [0] = ov772x */
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.flags = 0,
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.bus_width = 8,
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.bus_shift = 0,
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.i2c_adapter_id = 0,
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.i2c_address = 0x21,
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},
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{ /* [1] = tw9910 */
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.flags = 0,
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.bus_width = 8,
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.bus_shift = 0,
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.i2c_adapter_id = 0,
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.i2c_address = 0x45,
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},
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},
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};
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static struct resource migor_ceu_resources[] = {
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[0] = {
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.name = "CEU",
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.start = 0xfe910000,
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.end = 0xfe91009f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x880),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device migor_ceu_device = {
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.name = "renesas-ceu",
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.id = 0, /* ceu.0 */
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.num_resources = ARRAY_SIZE(migor_ceu_resources),
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.resource = migor_ceu_resources,
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.dev = {
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.platform_data = &ceu_pdata,
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},
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};
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/* Powerdown/reset gpios for CEU image sensors */
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static struct gpiod_lookup_table ov7725_gpios = {
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.dev_id = "0-0021",
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.table = {
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GPIO_LOOKUP("sh7722_pfc", GPIO_PTT0, "powerdown",
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GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "reset", GPIO_ACTIVE_LOW),
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},
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};
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static struct gpiod_lookup_table tw9910_gpios = {
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.dev_id = "0-0045",
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.table = {
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GPIO_LOOKUP("sh7722_pfc", GPIO_PTT2, "pdn", GPIO_ACTIVE_LOW),
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GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "rstb", GPIO_ACTIVE_LOW),
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},
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};
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/* Fixed 3.3V regulator to be used by SDHI0 */
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static struct regulator_consumer_supply fixed3v3_power_consumers[] =
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{
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REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
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REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
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};
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static struct resource sdhi_cn9_resources[] = {
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[0] = {
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.name = "SDHI",
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.start = 0x04ce0000,
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.end = 0x04ce00ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0xe80),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct tmio_mmc_data sh7724_sdhi_data = {
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.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
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.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
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.capabilities = MMC_CAP_SDIO_IRQ,
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};
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static struct platform_device sdhi_cn9_device = {
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.name = "sh_mobile_sdhi",
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.num_resources = ARRAY_SIZE(sdhi_cn9_resources),
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.resource = sdhi_cn9_resources,
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.dev = {
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.platform_data = &sh7724_sdhi_data,
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},
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};
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static struct ov772x_camera_info ov7725_info = {
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.flags = 0,
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};
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static struct tw9910_video_info tw9910_info = {
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.buswidth = 8,
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.mpout = TW9910_MPO_FIELD,
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};
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static struct i2c_board_info migor_i2c_devices[] = {
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{
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I2C_BOARD_INFO("rs5c372b", 0x32),
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},
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{
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I2C_BOARD_INFO("migor_ts", 0x51),
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.irq = evt2irq(0x6c0), /* IRQ6 */
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},
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{
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I2C_BOARD_INFO("wm8978", 0x1a),
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},
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{
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I2C_BOARD_INFO("ov772x", 0x21),
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.platform_data = &ov7725_info,
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},
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{
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I2C_BOARD_INFO("tw9910", 0x45),
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.platform_data = &tw9910_info,
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},
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};
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static struct platform_device *migor_devices[] __initdata = {
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&smc91x_eth_device,
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&sh_keysc_device,
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&migor_lcdc_device,
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&migor_nor_flash_device,
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&migor_nand_flash_device,
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&sdhi_cn9_device,
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};
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extern char migor_sdram_enter_start;
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extern char migor_sdram_enter_end;
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extern char migor_sdram_leave_start;
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extern char migor_sdram_leave_end;
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static int __init migor_devices_setup(void)
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{
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struct clk *video_clk;
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/* register board specific self-refresh code */
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sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
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&migor_sdram_enter_start,
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&migor_sdram_enter_end,
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&migor_sdram_leave_start,
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&migor_sdram_leave_end);
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regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
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ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
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/* Let D11 LED show STATUS0 */
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gpio_request(GPIO_FN_STATUS0, NULL);
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/* Lit D12 LED show PDSTATUS */
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gpio_request(GPIO_FN_PDSTATUS, NULL);
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/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
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gpio_request(GPIO_FN_IRQ0, NULL);
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__raw_writel(0x00003400, BSC_CS4BCR);
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__raw_writel(0x00110080, BSC_CS4WCR);
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/* KEYSC */
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gpio_request(GPIO_FN_KEYOUT0, NULL);
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gpio_request(GPIO_FN_KEYOUT1, NULL);
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gpio_request(GPIO_FN_KEYOUT2, NULL);
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gpio_request(GPIO_FN_KEYOUT3, NULL);
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gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
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gpio_request(GPIO_FN_KEYIN1, NULL);
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gpio_request(GPIO_FN_KEYIN2, NULL);
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gpio_request(GPIO_FN_KEYIN3, NULL);
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gpio_request(GPIO_FN_KEYIN4, NULL);
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gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
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/* NAND Flash */
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gpio_request(GPIO_FN_CS6A_CE2B, NULL);
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__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
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gpio_request(GPIO_PTA1, NULL);
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gpio_direction_input(GPIO_PTA1);
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/* SDHI */
|
|
gpio_request(GPIO_FN_SDHICD, NULL);
|
|
gpio_request(GPIO_FN_SDHIWP, NULL);
|
|
gpio_request(GPIO_FN_SDHID3, NULL);
|
|
gpio_request(GPIO_FN_SDHID2, NULL);
|
|
gpio_request(GPIO_FN_SDHID1, NULL);
|
|
gpio_request(GPIO_FN_SDHID0, NULL);
|
|
gpio_request(GPIO_FN_SDHICMD, NULL);
|
|
gpio_request(GPIO_FN_SDHICLK, NULL);
|
|
|
|
/* Touch Panel */
|
|
gpio_request(GPIO_FN_IRQ6, NULL);
|
|
|
|
/* LCD Panel */
|
|
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
|
|
gpio_request(GPIO_FN_LCDD17, NULL);
|
|
gpio_request(GPIO_FN_LCDD16, NULL);
|
|
gpio_request(GPIO_FN_LCDD15, NULL);
|
|
gpio_request(GPIO_FN_LCDD14, NULL);
|
|
gpio_request(GPIO_FN_LCDD13, NULL);
|
|
gpio_request(GPIO_FN_LCDD12, NULL);
|
|
gpio_request(GPIO_FN_LCDD11, NULL);
|
|
gpio_request(GPIO_FN_LCDD10, NULL);
|
|
gpio_request(GPIO_FN_LCDD8, NULL);
|
|
gpio_request(GPIO_FN_LCDD7, NULL);
|
|
gpio_request(GPIO_FN_LCDD6, NULL);
|
|
gpio_request(GPIO_FN_LCDD5, NULL);
|
|
gpio_request(GPIO_FN_LCDD4, NULL);
|
|
gpio_request(GPIO_FN_LCDD3, NULL);
|
|
gpio_request(GPIO_FN_LCDD2, NULL);
|
|
gpio_request(GPIO_FN_LCDD1, NULL);
|
|
gpio_request(GPIO_FN_LCDRS, NULL);
|
|
gpio_request(GPIO_FN_LCDCS, NULL);
|
|
gpio_request(GPIO_FN_LCDRD, NULL);
|
|
gpio_request(GPIO_FN_LCDWR, NULL);
|
|
gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
|
|
gpio_direction_output(GPIO_PTH2, 1);
|
|
#endif
|
|
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
|
|
gpio_request(GPIO_FN_LCDD15, NULL);
|
|
gpio_request(GPIO_FN_LCDD14, NULL);
|
|
gpio_request(GPIO_FN_LCDD13, NULL);
|
|
gpio_request(GPIO_FN_LCDD12, NULL);
|
|
gpio_request(GPIO_FN_LCDD11, NULL);
|
|
gpio_request(GPIO_FN_LCDD10, NULL);
|
|
gpio_request(GPIO_FN_LCDD9, NULL);
|
|
gpio_request(GPIO_FN_LCDD8, NULL);
|
|
gpio_request(GPIO_FN_LCDD7, NULL);
|
|
gpio_request(GPIO_FN_LCDD6, NULL);
|
|
gpio_request(GPIO_FN_LCDD5, NULL);
|
|
gpio_request(GPIO_FN_LCDD4, NULL);
|
|
gpio_request(GPIO_FN_LCDD3, NULL);
|
|
gpio_request(GPIO_FN_LCDD2, NULL);
|
|
gpio_request(GPIO_FN_LCDD1, NULL);
|
|
gpio_request(GPIO_FN_LCDD0, NULL);
|
|
gpio_request(GPIO_FN_LCDLCLK, NULL);
|
|
gpio_request(GPIO_FN_LCDDCK, NULL);
|
|
gpio_request(GPIO_FN_LCDVEPWC, NULL);
|
|
gpio_request(GPIO_FN_LCDVCPWC, NULL);
|
|
gpio_request(GPIO_FN_LCDVSYN, NULL);
|
|
gpio_request(GPIO_FN_LCDHSYN, NULL);
|
|
gpio_request(GPIO_FN_LCDDISP, NULL);
|
|
gpio_request(GPIO_FN_LCDDON, NULL);
|
|
#endif
|
|
|
|
/* CEU */
|
|
gpio_request(GPIO_FN_VIO_CLK2, NULL);
|
|
gpio_request(GPIO_FN_VIO_VD2, NULL);
|
|
gpio_request(GPIO_FN_VIO_HD2, NULL);
|
|
gpio_request(GPIO_FN_VIO_FLD, NULL);
|
|
gpio_request(GPIO_FN_VIO_CKO, NULL);
|
|
gpio_request(GPIO_FN_VIO_D15, NULL);
|
|
gpio_request(GPIO_FN_VIO_D14, NULL);
|
|
gpio_request(GPIO_FN_VIO_D13, NULL);
|
|
gpio_request(GPIO_FN_VIO_D12, NULL);
|
|
gpio_request(GPIO_FN_VIO_D11, NULL);
|
|
gpio_request(GPIO_FN_VIO_D10, NULL);
|
|
gpio_request(GPIO_FN_VIO_D9, NULL);
|
|
gpio_request(GPIO_FN_VIO_D8, NULL);
|
|
|
|
__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
|
|
|
|
/* SIU: Port B */
|
|
gpio_request(GPIO_FN_SIUBOLR, NULL);
|
|
gpio_request(GPIO_FN_SIUBOBT, NULL);
|
|
gpio_request(GPIO_FN_SIUBISLD, NULL);
|
|
gpio_request(GPIO_FN_SIUBOSLD, NULL);
|
|
gpio_request(GPIO_FN_SIUMCKB, NULL);
|
|
|
|
/*
|
|
* The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
|
|
* output. Need only SIUB, set to output for master mode (table 34.2)
|
|
*/
|
|
__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
|
|
|
|
/*
|
|
* Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality
|
|
* issues on Panel Board V2.1.
|
|
*/
|
|
video_clk = clk_get(NULL, "video_clk");
|
|
if (!IS_ERR(video_clk)) {
|
|
clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000));
|
|
clk_put(video_clk);
|
|
}
|
|
|
|
/* Add a clock alias for ov7725 xclk source. */
|
|
clk_add_alias(NULL, "0-0021", "video_clk", NULL);
|
|
|
|
/* Register GPIOs for video sources. */
|
|
gpiod_add_lookup_table(&ov7725_gpios);
|
|
gpiod_add_lookup_table(&tw9910_gpios);
|
|
|
|
i2c_register_board_info(0, migor_i2c_devices,
|
|
ARRAY_SIZE(migor_i2c_devices));
|
|
|
|
/* Initialize CEU platform device separately to map memory first */
|
|
device_initialize(&migor_ceu_device.dev);
|
|
arch_setup_pdev_archdata(&migor_ceu_device);
|
|
dma_declare_coherent_memory(&migor_ceu_device.dev,
|
|
ceu_dma_membase, ceu_dma_membase,
|
|
ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1,
|
|
DMA_MEMORY_EXCLUSIVE);
|
|
|
|
platform_device_add(&migor_ceu_device);
|
|
|
|
return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
|
|
}
|
|
arch_initcall(migor_devices_setup);
|
|
|
|
/* Return the board specific boot mode pin configuration */
|
|
static int migor_mode_pins(void)
|
|
{
|
|
/* MD0=1, MD1=1, MD2=0: Clock Mode 3
|
|
* MD3=0: 16-bit Area0 Bus Width
|
|
* MD5=1: Little Endian
|
|
* TSTMD=1, MD8=0: Test Mode Disabled
|
|
*/
|
|
return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
|
|
}
|
|
|
|
/* Reserve a portion of memory for CEU buffers */
|
|
static void __init migor_mv_mem_reserve(void)
|
|
{
|
|
phys_addr_t phys;
|
|
phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
|
|
|
|
phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
|
|
memblock_free(phys, size);
|
|
memblock_remove(phys, size);
|
|
|
|
ceu_dma_membase = phys;
|
|
}
|
|
|
|
/*
|
|
* The Machine Vector
|
|
*/
|
|
static struct sh_machine_vector mv_migor __initmv = {
|
|
.mv_name = "Migo-R",
|
|
.mv_mode_pins = migor_mode_pins,
|
|
.mv_mem_reserve = migor_mv_mem_reserve,
|
|
};
|