358 lines
9.9 KiB
C
358 lines
9.9 KiB
C
/*
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* SH7203 and SH7263 Setup
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*
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* Copyright (C) 2007 - 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <linux/io.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
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USB, LCDC, CMT0, CMT1, BSC, WDT,
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MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
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ADC_ADI,
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IIC30, IIC31, IIC32, IIC33,
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SCIF0, SCIF1, SCIF2, SCIF3,
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SSU0, SSU1,
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SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
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/* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
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ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
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SRC, IEBI,
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/* interrupt groups */
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PINT,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
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INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
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INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
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INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
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INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
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INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
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INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
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INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
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INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
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INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
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INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
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INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
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INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
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INTC_IRQ(MTU0_VEF, 150),
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INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
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INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
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INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
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INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
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INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
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INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
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INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
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INTC_IRQ(MTU2_TCI3V, 165),
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INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
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INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
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INTC_IRQ(MTU2_TCI4V, 170),
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INTC_IRQ(ADC_ADI, 171),
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INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
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INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
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INTC_IRQ(IIC30, 176),
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INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
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INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
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INTC_IRQ(IIC31, 181),
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INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
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INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
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INTC_IRQ(IIC32, 186),
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INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
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INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
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INTC_IRQ(IIC33, 191),
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INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
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INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
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INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
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INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
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INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
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INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
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INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
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INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
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INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
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INTC_IRQ(SSU0, 210),
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INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
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INTC_IRQ(SSU1, 213),
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INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
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INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
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INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
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INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
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INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
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INTC_IRQ(RTC, 233),
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INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
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INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
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INTC_IRQ(RCAN0, 238),
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INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
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INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
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INTC_IRQ(RCAN1, 243),
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/* SH7263-specific trash */
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#ifdef CONFIG_CPU_SUBTYPE_SH7263
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INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
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INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
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INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
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INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
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INTC_IRQ(SDHI, 230),
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INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
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INTC_IRQ(SRC, 246),
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INTC_IRQ(IEBI, 247),
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#endif
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
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{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
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{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
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{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
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{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
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MTU2_VU } },
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{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
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MTU2_TCI4V } },
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{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
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{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
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{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
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#ifdef CONFIG_CPU_SUBTYPE_SH7203
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{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
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SSI3_SSII, 0 } },
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{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
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{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
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#else
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{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
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SSI3_SSII, ROMDEC } },
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{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
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{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
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#endif
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffe0808, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
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mask_registers, prio_registers, NULL);
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static struct plat_sci_port scif0_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif0_resources[] = {
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DEFINE_RES_MEM(0xfffe8000, 0x100),
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DEFINE_RES_IRQ(192),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.resource = scif0_resources,
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.num_resources = ARRAY_SIZE(scif0_resources),
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct plat_sci_port scif1_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif1_resources[] = {
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DEFINE_RES_MEM(0xfffe8800, 0x100),
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DEFINE_RES_IRQ(196),
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.resource = scif1_resources,
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.num_resources = ARRAY_SIZE(scif1_resources),
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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static struct plat_sci_port scif2_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif2_resources[] = {
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DEFINE_RES_MEM(0xfffe9000, 0x100),
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DEFINE_RES_IRQ(200),
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.resource = scif2_resources,
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.num_resources = ARRAY_SIZE(scif2_resources),
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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static struct plat_sci_port scif3_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif3_resources[] = {
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DEFINE_RES_MEM(0xfffe9800, 0x100),
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DEFINE_RES_IRQ(204),
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.resource = scif3_resources,
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.num_resources = ARRAY_SIZE(scif3_resources),
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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static struct sh_timer_config cmt_platform_data = {
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.channels_mask = 3,
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};
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static struct resource cmt_resources[] = {
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DEFINE_RES_MEM(0xfffec000, 0x10),
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DEFINE_RES_IRQ(142),
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DEFINE_RES_IRQ(143),
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};
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static struct platform_device cmt_device = {
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.name = "sh-cmt-16",
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.id = 0,
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.dev = {
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.platform_data = &cmt_platform_data,
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},
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.resource = cmt_resources,
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.num_resources = ARRAY_SIZE(cmt_resources),
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};
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static struct resource mtu2_resources[] = {
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DEFINE_RES_MEM(0xfffe4000, 0x400),
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DEFINE_RES_IRQ_NAMED(146, "tgi0a"),
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DEFINE_RES_IRQ_NAMED(153, "tgi1a"),
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};
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static struct platform_device mtu2_device = {
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.name = "sh-mtu2",
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.id = -1,
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.resource = mtu2_resources,
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.num_resources = ARRAY_SIZE(mtu2_resources),
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};
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xffff2000,
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.end = 0xffff2000 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Shared Period/Carry/Alarm IRQ */
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.start = 231,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct platform_device *sh7203_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&cmt_device,
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&mtu2_device,
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&rtc_device,
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};
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static int __init sh7203_devices_setup(void)
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{
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return platform_add_devices(sh7203_devices,
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ARRAY_SIZE(sh7203_devices));
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}
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arch_initcall(sh7203_devices_setup);
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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static struct platform_device *sh7203_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&cmt_device,
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&mtu2_device,
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};
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#define STBCR3 0xfffe0408
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#define STBCR4 0xfffe040c
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void __init plat_early_device_setup(void)
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{
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/* enable CMT clock */
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__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
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/* enable MTU2 clock */
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__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
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early_platform_add_devices(sh7203_early_devices,
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ARRAY_SIZE(sh7203_early_devices));
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}
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