160 lines
4.2 KiB
C
160 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6877-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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/* get spm power status struct to register inside clk_data */
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static struct pwr_status mm_pwr_stat = GATE_PWR_STAT(0xEF0,
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0xEF4, INV_OFS, BIT(18), BIT(18));
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static const struct mtk_gate_regs mm0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mm1_cg_regs = {
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.set_ofs = 0x1a4,
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.clr_ofs = 0x1a8,
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.sta_ofs = 0x1a0,
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};
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#define GATE_MM0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &mm_pwr_stat, \
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}
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#define GATE_MM1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &mm_pwr_stat, \
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}
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static const struct mtk_gate mm_clks[] = {
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/* MM0 */
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GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0",
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"disp0_ck"/* parent */, 0),
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GATE_MM0(CLK_MM_APB_BUS, "mm_apb_bus",
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"disp0_ck"/* parent */, 1),
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GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0",
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"disp0_ck"/* parent */, 2),
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GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0",
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"disp0_ck"/* parent */, 3),
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GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l",
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"disp0_ck"/* parent */, 4),
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GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0",
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"disp0_ck"/* parent */, 5),
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GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1",
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"disp0_ck"/* parent */, 6),
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GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0",
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"disp0_ck"/* parent */, 7),
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GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0",
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"disp0_ck"/* parent */, 8),
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GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0",
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"disp0_ck"/* parent */, 9),
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GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0",
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"disp0_ck"/* parent */, 10),
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GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra",
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"disp0_ck"/* parent */, 11),
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GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0",
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"disp0_ck"/* parent */, 13),
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GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0",
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"disp0_ck"/* parent */, 14),
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GATE_MM0(CLK_MM_DISP_SPR0, "mm_disp_spr0",
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"disp0_ck"/* parent */, 15),
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GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0",
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"disp0_ck"/* parent */, 16),
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GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common",
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"disp0_ck"/* parent */, 17),
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GATE_MM0(CLK_MM_DISP_CM0, "mm_disp_cm0",
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"disp0_ck"/* parent */, 18),
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GATE_MM0(CLK_MM_DSI0, "mm_dsi0",
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"disp0_ck"/* parent */, 19),
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GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals",
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"disp0_ck"/* parent */, 22),
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GATE_MM0(CLK_MM_DISP_DSC_WRAP, "mm_disp_dsc_wrap",
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"disp0_ck"/* parent */, 23),
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GATE_MM0(CLK_MM_SMI_IOMMU, "mm_smi_iommu",
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"disp0_ck"/* parent */, 24),
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GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l",
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"disp0_ck"/* parent */, 25),
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GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0",
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"disp0_ck"/* parent */, 26),
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/* MM1 */
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GATE_MM1(CLK_MM_DSI0_DSI_CK_DOMAIN, "mm_dsi0_dsi_domain",
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"disp0_ck"/* parent */, 0),
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GATE_MM1(CLK_MM_DISP_26M, "mm_disp_26m_ck",
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"disp0_ck"/* parent */, 10),
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};
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static int clk_mt6877_mm_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
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mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static const struct of_device_id of_match_clk_mt6877_mm[] = {
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{ .compatible = "mediatek,mt6877-dispsys", },
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{}
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};
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static struct platform_driver clk_mt6877_mm_drv = {
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.probe = clk_mt6877_mm_probe,
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.driver = {
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.name = "clk-mt6877-mm",
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.of_match_table = of_match_clk_mt6877_mm,
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},
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};
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static int __init clk_mt6877_mm_init(void)
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{
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return platform_driver_register(&clk_mt6877_mm_drv);
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}
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arch_initcall(clk_mt6877_mm_init);
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