180 lines
3.7 KiB
C
180 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/seq_file.h>
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#include <linux/delay.h>
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#ifdef CONFIG_MTK_DEVAPC
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#include <mt-plat/devapc_public.h>
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#endif
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#include <clk-mux.h>
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#include "clkdbg.h"
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#include "clkchk.h"
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#include "clkchk-mt6877.h"
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#include "clk-fmeter.h"
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static const struct regname *get_all_regnames(void)
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{
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return get_mt6877_all_reg_names();
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}
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/*
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* clkdbg dump all fmeter clks
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*/
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static const struct fmeter_clk *get_all_fmeter_clks(void)
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{
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return get_fmeter_clks();
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}
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static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
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{
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if (fclk->type == ABIST)
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return mt_get_abist_freq(fclk->id);
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else if (fclk->type == ABIST_2)
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return mt_get_abist2_freq(fclk->id);
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else if (fclk->type == CKGEN)
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return mt_get_ckgen_freq(fclk->id);
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else if (fclk->type == SUBSYS)
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return mt_get_subsys_freq(fclk->id);
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return 0;
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}
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/*
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* clkdbg dump_clks
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*/
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static const char * const *get_all_clk_names(void)
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{
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return get_mt6877_all_clk_names();
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}
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/*
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* clkchk pwr_state
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*/
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struct pvd_msk {
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const char *pvdname;
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enum PWR_STA_TYPE sta_type;
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u32 pwr_mask;
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};
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static struct pvd_msk pvd_pwr_mask[] = {
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{"adspsys", PWR_STA, 0x00400000},
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{"audiosys", PWR_STA, 0x00200000},
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{"gpu_pll_ctrl", XPU_PWR_STA, 0x0000003F},
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{"mfgcfg", XPU_PWR_STA, 0x0000003F},
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{"dispsys", PWR_STA, 0x00040000},
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{"imgsys1", PWR_STA, 0x00000200},
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{"imgsys2", PWR_STA, 0x00000400},
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{"vdecsys", PWR_STA, 0x00001000},
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{"vencsys", PWR_STA, 0x00004000},
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{"apu_conn2", OTHER_PWR_STA, 0x00000020},
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{"apu_conn1", OTHER_PWR_STA, 0x00000020},
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{"apu_vcore", OTHER_PWR_STA, 0x00000020},
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{"apu0", OTHER_PWR_STA, 0x00000020},
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{"apu1", OTHER_PWR_STA, 0x00000020},
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{"apu_mdla0", OTHER_PWR_STA, 0x00000020},
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{"camsys_main", PWR_STA, 0x00800000},
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{"camsys_rawa", PWR_STA, 0x01000000},
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{"camsys_rawb", PWR_STA, 0x02000000},
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{"ipesys", PWR_STA, 0x00000800},
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{"mdpsys", PWR_STA, 0x00040000},
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{},
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};
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/*
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* clkdbg setup clks
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*/
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void setup_provider_clk(struct provider_clk *pvdck)
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{
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int i;
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const char *pvdname = pvdck->provider_name;
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if (!pvdname)
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return;
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for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask) - 1; i++) {
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if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
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pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
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pvdck->sta_type = pvd_pwr_mask[i].sta_type;
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return;
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}
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}
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pvdck->pwr_mask = 0;
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pvdck->sta_type = PWR_STA;
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}
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/*
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* clkdbg pwr_status
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*/
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static u32 pwr_ofs[STA_NUM] = {
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[XPU_PWR_STA] = 0xEF8,
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[XPU_PWR_STA2] = 0xEFC,
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[PWR_STA] = 0xEF0,
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[PWR_STA2] = 0xEF4,
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[OTHER_PWR_STA] = 0x178,
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};
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static u32 pwr_sta[STA_NUM];
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u32 *get_spm_pwr_status_array(void)
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{
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static void __iomem *scpsys_base, *pwr_addr[STA_NUM];
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int i;
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for (i = 0; i < STA_NUM; i++) {
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if (!scpsys_base)
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scpsys_base = ioremap(0x10006000, PAGE_SIZE);
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if (pwr_ofs[i]) {
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pwr_addr[i] = scpsys_base + pwr_ofs[i];
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pwr_sta[i] = clk_readl(pwr_addr[i]);
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}
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}
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return pwr_sta;
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}
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/*
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* init functions
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*/
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static struct clkdbg_ops clkdbg_mt6877_ops = {
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.get_all_fmeter_clks = get_all_fmeter_clks,
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.prepare_fmeter = NULL,
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.unprepare_fmeter = NULL,
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.fmeter_freq = fmeter_freq_op,
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.get_all_regnames = get_all_regnames,
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.get_all_clk_names = get_all_clk_names,
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.get_pwr_names = NULL,
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.setup_provider_clk = setup_provider_clk,
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.get_spm_pwr_status_array = get_spm_pwr_status_array,
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};
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static void __init init_custom_cmds(void)
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{
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static const struct cmd_fn cmds[] = {
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{}
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};
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set_custom_cmds(cmds);
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}
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static int __init clkdbg_mt6877_init(void)
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{
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if (!of_machine_is_compatible("mediatek,MT6877"))
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return -ENODEV;
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init_custom_cmds();
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set_clkdbg_ops(&clkdbg_mt6877_ops);
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return 0;
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}
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subsys_initcall(clkdbg_mt6877_init);
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