431 lines
11 KiB
C
431 lines
11 KiB
C
/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <drm/drm_of.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/bridge/dw_hdmi.h>
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#include "rockchip_drm_drv.h"
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#include "rockchip_drm_vop.h"
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#define RK3288_GRF_SOC_CON6 0x025C
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#define RK3288_HDMI_LCDC_SEL BIT(4)
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#define RK3399_GRF_SOC_CON20 0x6250
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#define RK3399_HDMI_LCDC_SEL BIT(6)
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#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
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/**
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* struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
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* @lcdsel_grf_reg: grf register offset of lcdc select
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* @lcdsel_big: reg value of selecting vop big for HDMI
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* @lcdsel_lit: reg value of selecting vop little for HDMI
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*/
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struct rockchip_hdmi_chip_data {
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u32 lcdsel_grf_reg;
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u32 lcdsel_big;
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u32 lcdsel_lit;
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};
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struct rockchip_hdmi {
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struct device *dev;
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struct regmap *regmap;
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struct drm_encoder encoder;
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const struct rockchip_hdmi_chip_data *chip_data;
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struct clk *vpll_clk;
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struct clk *grf_clk;
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struct dw_hdmi *hdmi;
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};
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#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
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static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
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{
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27000000, {
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{ 0x00b3, 0x0000},
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{ 0x2153, 0x0000},
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{ 0x40f3, 0x0000}
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},
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}, {
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36000000, {
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{ 0x00b3, 0x0000},
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{ 0x2153, 0x0000},
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{ 0x40f3, 0x0000}
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},
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}, {
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40000000, {
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{ 0x00b3, 0x0000},
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{ 0x2153, 0x0000},
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{ 0x40f3, 0x0000}
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},
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}, {
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54000000, {
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{ 0x0072, 0x0001},
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{ 0x2142, 0x0001},
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{ 0x40a2, 0x0001},
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},
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}, {
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65000000, {
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{ 0x0072, 0x0001},
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{ 0x2142, 0x0001},
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{ 0x40a2, 0x0001},
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},
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}, {
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66000000, {
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{ 0x013e, 0x0003},
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{ 0x217e, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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74250000, {
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{ 0x0072, 0x0001},
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{ 0x2145, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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83500000, {
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{ 0x0072, 0x0001},
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},
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}, {
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108000000, {
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{ 0x0051, 0x0002},
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{ 0x2145, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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106500000, {
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{ 0x0051, 0x0002},
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{ 0x2145, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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146250000, {
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{ 0x0051, 0x0002},
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{ 0x2145, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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148500000, {
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{ 0x0051, 0x0003},
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{ 0x214c, 0x0003},
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{ 0x4064, 0x0003}
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},
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}, {
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~0UL, {
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{ 0x00a0, 0x000a },
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{ 0x2001, 0x000f },
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{ 0x4002, 0x000f },
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},
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}
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};
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static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{
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40000000, { 0x0018, 0x0018, 0x0018 },
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}, {
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65000000, { 0x0028, 0x0028, 0x0028 },
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}, {
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66000000, { 0x0038, 0x0038, 0x0038 },
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}, {
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74250000, { 0x0028, 0x0038, 0x0038 },
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}, {
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83500000, { 0x0028, 0x0038, 0x0038 },
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}, {
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146250000, { 0x0038, 0x0038, 0x0038 },
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}, {
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148500000, { 0x0000, 0x0038, 0x0038 },
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}, {
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~0UL, { 0x0000, 0x0000, 0x0000},
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}
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};
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static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
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/*pixelclk symbol term vlev*/
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{ 74250000, 0x8009, 0x0004, 0x0272},
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{ 148500000, 0x802b, 0x0004, 0x028d},
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{ 297000000, 0x8039, 0x0005, 0x028d},
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
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{
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struct device_node *np = hdmi->dev->of_node;
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hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
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if (IS_ERR(hdmi->regmap)) {
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DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
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return PTR_ERR(hdmi->regmap);
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}
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hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
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if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
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hdmi->vpll_clk = NULL;
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} else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else if (IS_ERR(hdmi->vpll_clk)) {
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DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
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return PTR_ERR(hdmi->vpll_clk);
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}
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hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
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if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
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hdmi->grf_clk = NULL;
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} else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else if (IS_ERR(hdmi->grf_clk)) {
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DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
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return PTR_ERR(hdmi->grf_clk);
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}
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return 0;
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}
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static enum drm_mode_status
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dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
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const struct drm_display_mode *mode)
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{
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const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
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int pclk = mode->clock * 1000;
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bool valid = false;
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int i;
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for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
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if (pclk == mpll_cfg[i].mpixelclock) {
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valid = true;
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break;
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}
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}
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return (valid) ? MODE_OK : MODE_BAD;
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}
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static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
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.destroy = drm_encoder_cleanup,
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};
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static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
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{
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}
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static bool
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dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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return true;
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}
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static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
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clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
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}
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static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
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{
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struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
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u32 val;
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int ret;
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ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
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if (ret)
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val = hdmi->chip_data->lcdsel_lit;
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else
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val = hdmi->chip_data->lcdsel_big;
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ret = clk_prepare_enable(hdmi->grf_clk);
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if (ret < 0) {
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DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
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return;
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}
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ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
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if (ret != 0)
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DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
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clk_disable_unprepare(hdmi->grf_clk);
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DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
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ret ? "LIT" : "BIG");
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}
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static int
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dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
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s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
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s->output_type = DRM_MODE_CONNECTOR_HDMIA;
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return 0;
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}
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static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
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.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
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.mode_set = dw_hdmi_rockchip_encoder_mode_set,
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.enable = dw_hdmi_rockchip_encoder_enable,
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.disable = dw_hdmi_rockchip_encoder_disable,
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.atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
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};
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static struct rockchip_hdmi_chip_data rk3288_chip_data = {
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.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
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.lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
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};
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static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
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.mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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.phy_data = &rk3288_chip_data,
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};
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static struct rockchip_hdmi_chip_data rk3399_chip_data = {
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.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
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.lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
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};
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static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
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.mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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.phy_data = &rk3399_chip_data,
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};
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static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
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{ .compatible = "rockchip,rk3288-dw-hdmi",
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.data = &rk3288_hdmi_drv_data
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},
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{ .compatible = "rockchip,rk3399-dw-hdmi",
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.data = &rk3399_hdmi_drv_data
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
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static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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const struct dw_hdmi_plat_data *plat_data;
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const struct of_device_id *match;
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struct drm_device *drm = data;
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struct drm_encoder *encoder;
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struct rockchip_hdmi *hdmi;
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int ret;
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if (!pdev->dev.of_node)
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return -ENODEV;
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hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
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if (!hdmi)
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return -ENOMEM;
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match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
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plat_data = match->data;
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hdmi->dev = &pdev->dev;
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hdmi->chip_data = plat_data->phy_data;
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encoder = &hdmi->encoder;
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encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
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/*
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* If we failed to find the CRTC(s) which this encoder is
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* supposed to be connected to, it's because the CRTC has
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* not been registered yet. Defer probing, and hope that
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* the required CRTC is added later.
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*/
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if (encoder->possible_crtcs == 0)
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return -EPROBE_DEFER;
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ret = rockchip_hdmi_parse_dt(hdmi);
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if (ret) {
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DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
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return ret;
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}
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ret = clk_prepare_enable(hdmi->vpll_clk);
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if (ret) {
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DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
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ret);
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return ret;
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}
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drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
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drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
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DRM_MODE_ENCODER_TMDS, NULL);
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platform_set_drvdata(pdev, hdmi);
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hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
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/*
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* If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
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* which would have called the encoder cleanup. Do it manually.
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*/
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if (IS_ERR(hdmi->hdmi)) {
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ret = PTR_ERR(hdmi->hdmi);
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drm_encoder_cleanup(encoder);
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clk_disable_unprepare(hdmi->vpll_clk);
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}
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return ret;
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}
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static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
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dw_hdmi_unbind(hdmi->hdmi);
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clk_disable_unprepare(hdmi->vpll_clk);
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}
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static const struct component_ops dw_hdmi_rockchip_ops = {
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.bind = dw_hdmi_rockchip_bind,
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.unbind = dw_hdmi_rockchip_unbind,
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};
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static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
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}
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static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
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return 0;
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}
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struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
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.probe = dw_hdmi_rockchip_probe,
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.remove = dw_hdmi_rockchip_remove,
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.driver = {
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.name = "dwhdmi-rockchip",
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.of_match_table = dw_hdmi_rockchip_dt_ids,
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},
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};
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