198 lines
5.2 KiB
C
198 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __RT9471_CHARGER_H
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#define __RT9471_CHARGER_H
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#define RT9471_SLAVE_ADDR 0x53
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#define RT9470_DEVID 0x09
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#define RT9470D_DEVID 0x0A
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#define RT9471_DEVID 0x0D
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#define RT9471D_DEVID 0x0E
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enum rt9471_reg_addr {
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RT9471_REG_OTGCFG = 0x00,
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RT9471_REG_TOP,
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RT9471_REG_FUNCTION,
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RT9471_REG_IBUS,
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RT9471_REG_VBUS,
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RT9471_REG_PRECHG,
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RT9471_REG_REGU,
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RT9471_REG_VCHG,
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RT9471_REG_ICHG,
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RT9471_REG_CHGTIMER,
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RT9471_REG_EOC,
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RT9471_REG_INFO,
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RT9471_REG_JEITA,
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RT9471_REG_PUMPEXP,
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RT9471_REG_DPDMDET,
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RT9471_REG_STATUS,
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RT9471_REG_STAT0,
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RT9471_REG_STAT1,
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RT9471_REG_STAT2,
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RT9471_REG_STAT3,
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RT9471_REG_IRQ0 = 0x20,
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RT9471_REG_IRQ1,
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RT9471_REG_IRQ2,
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RT9471_REG_IRQ3,
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RT9471_REG_MASK0 = 0x30,
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RT9471_REG_MASK1,
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RT9471_REG_MASK2,
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RT9471_REG_MASK3,
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RT9471_REG_HIDDEN_0 = 0x40,
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RT9471_REG_HIDDEN_2 = 0x42,
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RT9471_REG_TOP_HDEN,
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RT9471_REG_BUCK_HDEN1 = 0x45,
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RT9471_REG_BUCK_HDEN2 = 0x46,
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RT9471_REG_BUCK_HDEN3 = 0x54,
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RT9471_REG_BUCK_HDEN4,
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RT9471_REG_OTG_HDEN2 = 0x58,
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RT9471_REG_BUCK_HDEN5,
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RT9471_REG_PASSCODE1 = 0xA0,
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};
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/* ========== OTGCFG 0x00 ============ */
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#define RT9471_OTGCC_MASK BIT(0)
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/* ========== TOP 0x01 ============ */
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#define RT9471_QONRST_MASK BIT(7)
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#define RT9471_DISI2CTO_MASK BIT(3)
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#define RT9471_WDTCNTRST_MASK BIT(2)
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#define RT9471_WDT_SHIFT 0
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#define RT9471_WDT_MASK 0x03
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/* ========== FUNCTION 0x02 ============ */
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#define RT9471_BATFETDIS_SHIFT 7
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#define RT9471_BATFETDIS_MASK BIT(7)
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#define RT9471_OTG_EN_SHIFT 1
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#define RT9471_OTG_EN_MASK BIT(1)
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#define RT9471_CHG_EN_SHIFT 0
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#define RT9471_CHG_EN_MASK BIT(0)
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/* ========== IBUS 0x03 ============ */
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#define RT9471_AICC_EN_SHIFT 7
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#define RT9471_AICC_EN_MASK BIT(7)
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#define RT9471_AUTOAICR_MASK BIT(6)
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#define RT9471_AICR_SHIFT 0
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#define RT9471_AICR_MASK 0x3F
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#define RT9471_AICR_MIN 50000
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#define RT9471_AICR_MAX 3200000
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#define RT9471_AICR_STEP 50000
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/* ========== VBUS 0x04 ============ */
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#define RT9471_VAC_OVP_SHIFT 6
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#define RT9471_VAC_OVP_MASK 0xC0
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#define RT9471_MIVR_SHIFT 0
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#define RT9471_MIVR_MASK 0x0F
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#define RT9471_MIVR_MIN 3900000
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#define RT9471_MIVR_MAX 5400000
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#define RT9471_MIVR_STEP 100000
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#define RT9471_MIVRTRACK_SHIFT 4
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#define RT9471_MIVRTRACK_MASK 0x30
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/* ========== VCHG 0x07 ============ */
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#define RT9471_VRECHG_MASK BIT(7)
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#define RT9471_CV_SHIFT 0
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#define RT9471_CV_MASK 0x7F
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#define RT9471_CV_MIN 3900000
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#define RT9471_CV_MAX 4700000
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#define RT9471_CV_STEP 10000
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/* ========== ICHG 0x08 ============ */
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#define RT9471_ICHG_SHIFT 0
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#define RT9471_ICHG_MASK 0x3F
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#define RT9471_ICHG_MIN 0
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#define RT9471_ICHG_MAX 3150000
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#define RT9471_ICHG_STEP 50000
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/* ========== CHGTIMER 0x09 ============ */
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#define RT9471_SAFETMR_EN_SHIFT 7
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#define RT9471_SAFETMR_EN_MASK BIT(7)
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#define RT9471_SAFETMR_SHIFT 4
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#define RT9471_SAFETMR_MASK 0x30
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#define RT9471_SAFETMR_MIN 5
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#define RT9471_SAFETMR_MAX 20
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#define RT9471_SAFETMR_STEP 5
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/* ========== EOC 0x0A ============ */
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#define RT9471_IEOC_SHIFT 4
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#define RT9471_IEOC_MASK 0xF0
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#define RT9471_IEOC_MIN 50000
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#define RT9471_IEOC_MAX 800000
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#define RT9471_IEOC_STEP 50000
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#define RT9471_TE_MASK BIT(1)
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#define RT9471_EOC_RST_SHIFT 0
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#define RT9471_EOC_RST_MASK BIT(0)
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/* ========== INFO 0x0B ============ */
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#define RT9471_REGRST_MASK BIT(7)
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#define RT9471_DEVID_SHIFT 3
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#define RT9471_DEVID_MASK 0x78
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#define RT9471_DEVREV_SHIFT 0
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#define RT9471_DEVREV_MASK 0x03
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/* ========== JEITA 0x0C ============ */
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#define RT9471_JEITA_EN_MASK BIT(7)
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/* ========== PUMPEXP 0x0D ============ */
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#define RT9471_PE_EN_MASK BIT(7)
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#define RT9471_PE_SEL_MASK BIT(6)
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#define RT9471_PE10_INC_MASK BIT(5)
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#define RT9471_PE20_CODE_SHIFT 0
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#define RT9471_PE20_CODE_MASK 0x1F
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#define RT9471_PE20_CODE_MIN 5500000
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#define RT9471_PE20_CODE_MAX 20000000
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#define RT9471_PE20_CODE_STEP 500000
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/* ========== DPDMDET 0x0E ============ */
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#define RT9471_BC12_EN_MASK BIT(7)
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/* ========== STATUS 0x0F ============ */
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#define RT9471_ICSTAT_SHIFT 0
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#define RT9471_ICSTAT_MASK 0x0F
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#define RT9471_PORTSTAT_SHIFT 4
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#define RT9471_PORTSTAT_MASK 0xF0
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/* ========== STAT0 0x10 ============ */
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#define RT9471_ST_VBUSGD_SHIFT 7
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#define RT9471_ST_VBUSGD_MASK BIT(7)
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#define RT9471_ST_CHGRDY_SHIFT 6
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#define RT9471_ST_CHGRDY_MASK BIT(6)
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#define RT9471_ST_CHGDONE_SHIFT 3
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#define RT9471_ST_CHGDONE_MASK BIT(3)
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#define RT9471_ST_BC12_DONE_SHIFT 0
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#define RT9471_ST_BC12_DONE_MASK BIT(0)
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/* ========== STAT1 0x11 ============ */
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#define RT9471_ST_MIVR_SHIFT 7
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#define RT9471_ST_MIVR_MASK BIT(7)
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#define RT9471_ST_AICR_MASK BIT(6)
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#define RT9471_ST_BATOV_MASK BIT(1)
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/* ========== STAT2 0x12 ============ */
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#define RT9471_ST_SYSMIN_SHIFT 1
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/* ========== STAT3 0x13 ============ */
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#define RT9471_ST_VACOV_SHIFT 6
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#define RT9471_ST_VACOV_MASK BIT(6)
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/* ========== HIDDEN_0 0x40 ============ */
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#define RT9471_CHIP_REV_SHIFT 5
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#define RT9471_CHIP_REV_MASK 0xE0
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/* ========== HIDDEN_2 0x42 ============ */
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#define RT9471_FORCE_HZ_SHIFT 2
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#define RT9471_FORCE_HZ_MASK BIT(2)
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/* ========== TOP_HDEN 0x43 ============ */
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#define RT9471_FORCE_EN_VBUS_SINK_SHIFT 4
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#define RT9471_FORCE_EN_VBUS_SINK_MASK BIT(4)
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/* ========== OTG_HDEN2 0x58 ============ */
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#define RT9471_REG_OTG_RES_COMP_SHIFT 4
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#define RT9471_REG_OTG_RES_COMP_MASK 0x30
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#endif /* __RT9471_CHARGER_H */
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