767 lines
22 KiB
C
767 lines
22 KiB
C
/*
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* Copyright (C) STMicroelectronics 2009
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License v2
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* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
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*
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* PRCMU f/w APIs
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*/
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#ifndef __MFD_DB8500_PRCMU_H
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#define __MFD_DB8500_PRCMU_H
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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/*
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* Registers
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*/
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#define DB8500_PRCM_LINE_VALUE 0x170
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#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
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#define DB8500_PRCM_DSI_SW_RESET 0x324
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#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
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#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
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#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
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/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
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/**
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* enum state - ON/OFF state definition
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* @OFF: State is ON
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* @ON: State is OFF
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*
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*/
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enum state {
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OFF = 0x0,
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ON = 0x1,
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};
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/**
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* enum ret_state - general purpose On/Off/Retention states
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*
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*/
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enum ret_state {
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OFFST = 0,
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ONST = 1,
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RETST = 2
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};
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/**
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* enum clk_arm - ARM Cortex A9 clock schemes
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* @A9_OFF:
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* @A9_BOOT:
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* @A9_OPPT1:
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* @A9_OPPT2:
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* @A9_EXTCLK:
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*/
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enum clk_arm {
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A9_OFF,
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A9_BOOT,
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A9_OPPT1,
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A9_OPPT2,
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A9_EXTCLK
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};
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/**
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* enum clk_gen - GEN#0/GEN#1 clock schemes
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* @GEN_OFF:
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* @GEN_BOOT:
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* @GEN_OPPT1:
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*/
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enum clk_gen {
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GEN_OFF,
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GEN_BOOT,
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GEN_OPPT1,
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};
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/* some information between arm and xp70 */
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/**
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* enum romcode_write - Romcode message written by A9 AND read by XP70
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* @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
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* @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
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* romcode. The xp70 will go into self-reset
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*/
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enum romcode_write {
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RDY_2_DS = 0x09,
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RDY_2_XP70_RST = 0x10
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};
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/**
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* enum romcode_read - Romcode message written by XP70 and read by A9
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* @INIT: Init value when romcode field is not used
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* @FS_2_DS: Value set when power state is going from ApExecute to
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* ApDeepSleep
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* @END_DS: Value set when ApDeepSleep power state is reached coming from
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* ApExecute state
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* @DS_TO_FS: Value set when power state is going from ApDeepSleep to
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* ApExecute
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* @END_FS: Value set when ApExecute power state is reached coming from
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* ApDeepSleep state
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* @SWR: Value set when power state is going to ApReset
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* @END_SWR: Value set when the xp70 finished executing ApReset actions and
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* waits for romcode acknowledgment to go to self-reset
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*/
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enum romcode_read {
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INIT = 0x00,
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FS_2_DS = 0x0A,
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END_DS = 0x0B,
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DS_TO_FS = 0x0C,
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END_FS = 0x0D,
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SWR = 0x0E,
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END_SWR = 0x0F
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};
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/**
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* enum ap_pwrst - current power states defined in PRCMU firmware
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* @NO_PWRST: Current power state init
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* @AP_BOOT: Current power state is apBoot
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* @AP_EXECUTE: Current power state is apExecute
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* @AP_DEEP_SLEEP: Current power state is apDeepSleep
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* @AP_SLEEP: Current power state is apSleep
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* @AP_IDLE: Current power state is apIdle
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* @AP_RESET: Current power state is apReset
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*/
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enum ap_pwrst {
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NO_PWRST = 0x00,
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AP_BOOT = 0x01,
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AP_EXECUTE = 0x02,
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AP_DEEP_SLEEP = 0x03,
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AP_SLEEP = 0x04,
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AP_IDLE = 0x05,
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AP_RESET = 0x06
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};
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/**
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* enum ap_pwrst_trans - Transition states defined in PRCMU firmware
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* @NO_TRANSITION: No power state transition
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* @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
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* @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
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* @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
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* @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
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* ApDeepSleep
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* @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
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*/
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enum ap_pwrst_trans {
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PRCMU_AP_NO_CHANGE = 0x00,
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APEXECUTE_TO_APSLEEP = 0x01,
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APIDLE_TO_APSLEEP = 0x02, /* To be removed */
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PRCMU_AP_SLEEP = 0x01,
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APBOOT_TO_APEXECUTE = 0x03,
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APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
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PRCMU_AP_DEEP_SLEEP = 0x04,
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APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
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PRCMU_AP_IDLE = 0x05,
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PRCMU_AP_DEEP_IDLE = 0x07,
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};
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/**
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* enum hw_acc_state - State definition for hardware accelerator
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* @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
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* @HW_OFF: The hardware accelerator must be switched off
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* @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
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* internal RAM in retention
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* @HW_ON: The hwa hardware accelerator hwa must be switched on
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*
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* NOTE! Deprecated, to be removed when all users switched over to use the
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* regulator API.
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*/
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enum hw_acc_state {
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HW_NO_CHANGE = 0x00,
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HW_OFF = 0x01,
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HW_OFF_RAMRET = 0x02,
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HW_ON = 0x04
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};
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/**
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* enum mbox_2_arm_stat - Status messages definition for mbox_arm
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* @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
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* completed
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* @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
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* completed
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* @SLEEPOK: The apExecute to apSleep state transition has been completed
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* @IDLEOK: The apExecute to apIdle state transition has been completed
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* @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
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* @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
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* @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
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* @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
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* going
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* @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
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* going
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* @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
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* been completed
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* @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
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* @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
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* @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
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* completed
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* @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
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* @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
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* @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
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* completed
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* @INIT_STATUS: Status init
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*/
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enum ap_pwrsttr_status {
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BOOT_TO_EXECUTEOK = 0xFF,
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DEEPSLEEPOK = 0xFE,
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SLEEPOK = 0xFD,
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IDLEOK = 0xFC,
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SOFTRESETOK = 0xFB,
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SOFTRESETGO = 0xFA,
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BOOT_TO_EXECUTE = 0xF9,
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EXECUTE_TO_DEEPSLEEP = 0xF8,
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DEEPSLEEP_TO_EXECUTE = 0xF7,
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DEEPSLEEP_TO_EXECUTEOK = 0xF6,
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EXECUTE_TO_SLEEP = 0xF5,
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SLEEP_TO_EXECUTE = 0xF4,
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SLEEP_TO_EXECUTEOK = 0xF3,
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EXECUTE_TO_IDLE = 0xF2,
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IDLE_TO_EXECUTE = 0xF1,
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IDLE_TO_EXECUTEOK = 0xF0,
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RDYTODS_RETURNTOEXE = 0xEF,
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NORDYTODS_RETURNTOEXE = 0xEE,
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EXETOSLEEP_RETURNTOEXE = 0xED,
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EXETOIDLE_RETURNTOEXE = 0xEC,
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INIT_STATUS = 0xEB,
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/*error messages */
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INITERROR = 0x00,
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PLLARMLOCKP_ER = 0x01,
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PLLDDRLOCKP_ER = 0x02,
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PLLSOCLOCKP_ER = 0x03,
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PLLSOCK1LOCKP_ER = 0x04,
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ARMWFI_ER = 0x05,
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SYSCLKOK_ER = 0x06,
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I2C_NACK_DATA_ER = 0x07,
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BOOT_ER = 0x08,
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I2C_STATUS_ALWAYS_1 = 0x0A,
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I2C_NACK_REG_ADDR_ER = 0x0B,
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I2C_NACK_DATA0123_ER = 0x1B,
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I2C_NACK_ADDR_ER = 0x1F,
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CURAPPWRSTISNOT_BOOT = 0x20,
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CURAPPWRSTISNOT_EXECUTE = 0x21,
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CURAPPWRSTISNOT_SLEEPMODE = 0x22,
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CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
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FIFO4500WUISNOT_WUPEVENT = 0x24,
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PLL32KLOCKP_ER = 0x29,
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DDRDEEPSLEEPOK_ER = 0x2A,
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ROMCODEREADY_ER = 0x50,
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WUPBEFOREDS = 0x51,
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DDRCONFIG_ER = 0x52,
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WUPBEFORESLEEP = 0x53,
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WUPBEFOREIDLE = 0x54
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}; /* earlier called as mbox_2_arm_stat */
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/**
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* enum dvfs_stat - DVFS status messages definition
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* @DVFS_GO: A state transition DVFS is on going
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* @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
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* @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
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* @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
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* @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
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* NOCHGCLK
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* @DVFS_INITSTATUS: Value init
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*/
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enum dvfs_stat {
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DVFS_GO = 0xFF,
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DVFS_ARM100OPPOK = 0xFE,
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DVFS_ARM50OPPOK = 0xFD,
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DVFS_ARMEXTCLKOK = 0xFC,
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DVFS_NOCHGTCLKOK = 0xFB,
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DVFS_INITSTATUS = 0x00
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};
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/**
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* enum sva_mmdsp_stat - SVA MMDSP status messages
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* @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
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* @SVA_MMDSP_INIT: Status init
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*/
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enum sva_mmdsp_stat {
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SVA_MMDSP_GO = 0xFF,
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SVA_MMDSP_INIT = 0x00
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};
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/**
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* enum sia_mmdsp_stat - SIA MMDSP status messages
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* @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
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* @SIA_MMDSP_INIT: Status init
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*/
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enum sia_mmdsp_stat {
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SIA_MMDSP_GO = 0xFF,
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SIA_MMDSP_INIT = 0x00
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};
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/**
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* enum mbox_to_arm_err - Error messages definition
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* @INIT_ERR: Init value
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* @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
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* @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
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* @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
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* @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
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* @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
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* @SYSCLKOK_ERR: The SYSCLK is not available in the given time
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* @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
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* @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
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* @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
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* through I2C has not been correctly executed in the given time
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* @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
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* through I2C has not been correctly executed in the given time
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* @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
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* I2C has not been correctly executed in the given time
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* @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
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* through I2C has not been correctly executed in the given time
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* @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
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* I2C has not been correctly executed in the given time
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* @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
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* through I2C has not been correctly executed in the given time
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* @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
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* I2C has not been correctly executed in the given time
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* @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
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* has not been correctly executed in the given time
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* @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
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* not been correctly executed in the given time
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* @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
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* not been correctly executed in the given time
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* @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
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* I2C has not been correctly executed in the given time
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* @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
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* I2C has not been correctly executed in the given time
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* @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
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* through I2C has not been correctly executed in the given time
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* @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
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* ApBoot to ApExecute but the power current state is not Apboot
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* @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
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* transition from ApExecute to others power state but the
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* power current state is not ApExecute
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* @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
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* but the power current state is not ApDeepSleep/ApSleep/ApIdle
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* @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
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* but the power current state is not correct
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* @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
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* been correctly executed in the given time
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* @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
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* been correctly executed in the given time
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* @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
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* been correctly executed in the given time
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* @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
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* been correctly executed in the given time
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* @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
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* been correctly executed in the given time
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*/
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enum mbox_to_arm_err {
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INIT_ERR = 0x00,
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PLLARMLOCKP_ERR = 0x01,
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PLLDDRLOCKP_ERR = 0x02,
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PLLSOC0LOCKP_ERR = 0x03,
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PLLSOC1LOCKP_ERR = 0x04,
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ARMWFI_ERR = 0x05,
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SYSCLKOK_ERR = 0x06,
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BOOT_ERR = 0x07,
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ROMCODESAVECONTEXT = 0x08,
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VARMHIGHSPEEDVALTO_ERR = 0x10,
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VARMHIGHSPEEDACCESS_ERR = 0x11,
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VARMLOWSPEEDVALTO_ERR = 0x12,
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VARMLOWSPEEDACCESS_ERR = 0x13,
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VARMRETENTIONVALTO_ERR = 0x14,
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VARMRETENTIONACCESS_ERR = 0x15,
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VAPEHIGHSPEEDVALTO_ERR = 0x16,
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VSAFEHPVALTO_ERR = 0x17,
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VMODSEL1VALTO_ERR = 0x18,
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VMODSEL2VALTO_ERR = 0x19,
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VARMOFFACCESS_ERR = 0x1A,
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VAPEOFFACCESS_ERR = 0x1B,
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VARMRETACCES_ERR = 0x1C,
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CURAPPWRSTISNOTBOOT = 0x20,
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CURAPPWRSTISNOTEXECUTE = 0x21,
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CURAPPWRSTISNOTSLEEPMODE = 0x22,
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CURAPPWRSTISNOTCORRECTDBG = 0x23,
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ARMREGU1VALTO_ERR = 0x24,
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ARMREGU2VALTO_ERR = 0x25,
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VAPEREGUVALTO_ERR = 0x26,
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VSMPS3REGUVALTO_ERR = 0x27,
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VMODREGUVALTO_ERR = 0x28
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};
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enum hw_acc {
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SVAMMDSP = 0,
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SVAPIPE = 1,
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SIAMMDSP = 2,
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SIAPIPE = 3,
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SGA = 4,
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B2R2MCDE = 5,
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ESRAM12 = 6,
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ESRAM34 = 7,
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};
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enum cs_pwrmgt {
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PWRDNCS0 = 0,
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WKUPCS0 = 1,
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PWRDNCS1 = 2,
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WKUPCS1 = 3
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};
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/* Defs related to autonomous power management */
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/**
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* enum sia_sva_pwr_policy - Power policy
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* @NO_CHGT: No change
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* @DSPOFF_HWPOFF:
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* @DSPOFFRAMRET_HWPOFF:
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* @DSPCLKOFF_HWPOFF:
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* @DSPCLKOFF_HWPCLKOFF:
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*
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*/
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enum sia_sva_pwr_policy {
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NO_CHGT = 0x0,
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DSPOFF_HWPOFF = 0x1,
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DSPOFFRAMRET_HWPOFF = 0x2,
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DSPCLKOFF_HWPOFF = 0x3,
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DSPCLKOFF_HWPCLKOFF = 0x4,
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};
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/**
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* enum auto_enable - Auto Power enable
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* @AUTO_OFF:
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* @AUTO_ON:
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*
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*/
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enum auto_enable {
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AUTO_OFF = 0x0,
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AUTO_ON = 0x1,
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};
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/* End of file previously known as prcmu-fw-defs_v1.h */
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/**
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* enum prcmu_power_status - results from set_power_state
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* @PRCMU_SLEEP_OK: Sleep went ok
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* @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
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* @PRCMU_IDLE_OK: Idle went ok
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* @PRCMU_DEEPIDLE_OK: DeepIdle went ok
|
|
* @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
|
|
* @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
|
|
*
|
|
*/
|
|
enum prcmu_power_status {
|
|
PRCMU_SLEEP_OK = 0xf3,
|
|
PRCMU_DEEP_SLEEP_OK = 0xf6,
|
|
PRCMU_IDLE_OK = 0xf0,
|
|
PRCMU_DEEPIDLE_OK = 0xe3,
|
|
PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
|
|
PRCMU_ARMPENDINGIT_ER = 0x93,
|
|
};
|
|
|
|
/*
|
|
* Definitions for autonomous power management configuration.
|
|
*/
|
|
|
|
#define PRCMU_AUTO_PM_OFF 0
|
|
#define PRCMU_AUTO_PM_ON 1
|
|
|
|
#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
|
|
#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
|
|
|
|
enum prcmu_auto_pm_policy {
|
|
PRCMU_AUTO_PM_POLICY_NO_CHANGE,
|
|
PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
|
|
PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
|
|
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
|
|
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
|
|
};
|
|
|
|
/**
|
|
* struct prcmu_auto_pm_config - Autonomous power management configuration.
|
|
* @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
|
|
* @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
|
|
* @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
|
|
* @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
|
|
* @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
|
|
* @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
|
|
*/
|
|
struct prcmu_auto_pm_config {
|
|
u8 sia_auto_pm_enable;
|
|
u8 sia_power_on;
|
|
u8 sia_policy;
|
|
u8 sva_auto_pm_enable;
|
|
u8 sva_power_on;
|
|
u8 sva_policy;
|
|
};
|
|
|
|
#ifdef CONFIG_MFD_DB8500_PRCMU
|
|
|
|
void db8500_prcmu_early_init(u32 phy_base, u32 size);
|
|
int prcmu_set_rc_a2p(enum romcode_write);
|
|
enum romcode_read prcmu_get_rc_p2a(void);
|
|
enum ap_pwrst prcmu_get_xp70_current_state(void);
|
|
bool prcmu_has_arm_maxopp(void);
|
|
struct prcmu_fw_version *prcmu_get_fw_version(void);
|
|
int prcmu_release_usb_wakeup_state(void);
|
|
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
|
|
struct prcmu_auto_pm_config *idle);
|
|
bool prcmu_is_auto_pm_enabled(void);
|
|
|
|
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
|
|
int prcmu_set_clock_divider(u8 clock, u8 divider);
|
|
int db8500_prcmu_config_hotdog(u8 threshold);
|
|
int db8500_prcmu_config_hotmon(u8 low, u8 high);
|
|
int db8500_prcmu_start_temp_sense(u16 cycles32k);
|
|
int db8500_prcmu_stop_temp_sense(void);
|
|
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
|
|
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
|
|
|
|
int prcmu_ac_wake_req(void);
|
|
void prcmu_ac_sleep_req(void);
|
|
void db8500_prcmu_modem_reset(void);
|
|
|
|
int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
|
|
int db8500_prcmu_enable_a9wdog(u8 id);
|
|
int db8500_prcmu_disable_a9wdog(u8 id);
|
|
int db8500_prcmu_kick_a9wdog(u8 id);
|
|
int db8500_prcmu_load_a9wdog(u8 id, u32 val);
|
|
|
|
void db8500_prcmu_system_reset(u16 reset_code);
|
|
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
|
|
u8 db8500_prcmu_get_power_state_result(void);
|
|
void db8500_prcmu_enable_wakeups(u32 wakeups);
|
|
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
|
|
int db8500_prcmu_request_clock(u8 clock, bool enable);
|
|
int db8500_prcmu_set_display_clocks(void);
|
|
int db8500_prcmu_disable_dsipll(void);
|
|
int db8500_prcmu_enable_dsipll(void);
|
|
void db8500_prcmu_config_abb_event_readout(u32 abb_events);
|
|
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
|
|
int db8500_prcmu_config_esram0_deep_sleep(u8 state);
|
|
u16 db8500_prcmu_get_reset_code(void);
|
|
bool db8500_prcmu_is_ac_wake_requested(void);
|
|
int db8500_prcmu_set_arm_opp(u8 opp);
|
|
int db8500_prcmu_get_arm_opp(void);
|
|
int db8500_prcmu_set_ape_opp(u8 opp);
|
|
int db8500_prcmu_get_ape_opp(void);
|
|
int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
|
|
int db8500_prcmu_get_ddr_opp(void);
|
|
|
|
u32 db8500_prcmu_read(unsigned int reg);
|
|
void db8500_prcmu_write(unsigned int reg, u32 value);
|
|
void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
|
|
|
|
#else /* !CONFIG_MFD_DB8500_PRCMU */
|
|
|
|
static inline void db8500_prcmu_early_init(u32 phy_base, u32 size) {}
|
|
|
|
static inline int prcmu_set_rc_a2p(enum romcode_write code)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline enum romcode_read prcmu_get_rc_p2a(void)
|
|
{
|
|
return INIT;
|
|
}
|
|
|
|
static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
|
|
{
|
|
return AP_EXECUTE;
|
|
}
|
|
|
|
static inline bool prcmu_has_arm_maxopp(void)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline int db8500_prcmu_set_ape_opp(u8 opp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_get_ape_opp(void)
|
|
{
|
|
return APE_100_OPP;
|
|
}
|
|
|
|
static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_release_usb_wakeup_state(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_get_ddr_opp(void)
|
|
{
|
|
return DDR_100_OPP;
|
|
}
|
|
|
|
static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
|
|
struct prcmu_auto_pm_config *idle)
|
|
{
|
|
}
|
|
|
|
static inline bool prcmu_is_auto_pm_enabled(void)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_config_hotdog(u8 threshold)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_stop_temp_sense(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static inline int prcmu_ac_wake_req(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void prcmu_ac_sleep_req(void) {}
|
|
|
|
static inline void db8500_prcmu_modem_reset(void) {}
|
|
|
|
static inline void db8500_prcmu_system_reset(u16 reset_code) {}
|
|
|
|
static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
|
bool keep_ap_pll)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 db8500_prcmu_get_power_state_result(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
|
|
|
|
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_set_display_clocks(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_disable_dsipll(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_enable_dsipll(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
|
|
|
|
static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
|
|
|
|
static inline u16 db8500_prcmu_get_reset_code(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_enable_a9wdog(u8 id)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_disable_a9wdog(u8 id)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_kick_a9wdog(u8 id)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline bool db8500_prcmu_is_ac_wake_requested(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_set_arm_opp(u8 opp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int db8500_prcmu_get_arm_opp(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 db8500_prcmu_read(unsigned int reg)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
|
|
|
|
static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
|
|
u32 value) {}
|
|
|
|
#endif /* !CONFIG_MFD_DB8500_PRCMU */
|
|
|
|
#endif /* __MFD_DB8500_PRCMU_H */
|