197 lines
6.7 KiB
Plaintext
197 lines
6.7 KiB
Plaintext
Mediatek display subsystem
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==========================
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The Mediatek display subsystem consists of various DISP function blocks in the
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MMSYS register space. The connections between them can be configured by output
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and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
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of frame signal are distributed to the other function blocks by a DISP_MUTEX
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function block.
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All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
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DISP function blocks
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====================
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A display stream starts at a source function block that reads pixel data from
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memory and ends with a sink function block that drives pixels on a display
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interface, or writes pixels back to memory. All DISP function blocks have
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their own register space, interrupt, and clock gate. The blocks that can
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access memory additionally have to list the IOMMU and local arbiter they are
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connected to.
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For a description of the display interface sink function blocks, see
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Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
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Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
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Required properties (all function blocks):
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- compatible: "mediatek,<chip>-disp-<function>", one of
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"mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
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"mediatek,<chip>-disp-rdma" - read DMA / line buffer
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"mediatek,<chip>-disp-wdma" - write DMA
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"mediatek,<chip>-disp-color" - color processor
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"mediatek,<chip>-disp-aal" - adaptive ambient light controller
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"mediatek,<chip>-disp-gamma" - gamma correction
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"mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
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"mediatek,<chip>-disp-split" - split stream to two encoders
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"mediatek,<chip>-disp-ufoe" - data compression engine
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"mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
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"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
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"mediatek,<chip>-disp-mutex" - display mutex
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"mediatek,<chip>-disp-od" - overdrive
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the supported chips are mt2701, mt2712 and mt8173.
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- reg: Physical base address and length of the function block register space
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- interrupts: The interrupt signal from the function block (required, except for
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merge and split function blocks).
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- clocks: device clocks
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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For most function blocks this is just a single clock input. Only the DSI and
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DPI controller nodes have multiple clock inputs. These are documented in
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mediatek,dsi.txt and mediatek,dpi.txt, respectively.
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Required properties (DMA function blocks):
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- compatible: Should be one of
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"mediatek,<chip>-disp-ovl"
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"mediatek,<chip>-disp-rdma"
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"mediatek,<chip>-disp-wdma"
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the supported chips are mt2701 and mt8173.
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- iommus: Should point to the respective IOMMU block with master port as
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argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
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for details.
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Examples:
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mmsys: clock-controller@14000000 {
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compatible = "mediatek,mt8173-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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#clock-cells = <1>;
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};
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ovl0: ovl@1400c000 {
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compatible = "mediatek,mt8173-disp-ovl";
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reg = <0 0x1400c000 0 0x1000>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_OVL0>;
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iommus = <&iommu M4U_PORT_DISP_OVL0>;
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};
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ovl1: ovl@1400d000 {
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compatible = "mediatek,mt8173-disp-ovl";
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reg = <0 0x1400d000 0 0x1000>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_OVL1>;
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iommus = <&iommu M4U_PORT_DISP_OVL1>;
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};
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rdma0: rdma@1400e000 {
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compatible = "mediatek,mt8173-disp-rdma";
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reg = <0 0x1400e000 0 0x1000>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA0>;
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iommus = <&iommu M4U_PORT_DISP_RDMA0>;
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};
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rdma1: rdma@1400f000 {
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compatible = "mediatek,mt8173-disp-rdma";
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reg = <0 0x1400f000 0 0x1000>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA1>;
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iommus = <&iommu M4U_PORT_DISP_RDMA1>;
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};
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rdma2: rdma@14010000 {
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compatible = "mediatek,mt8173-disp-rdma";
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reg = <0 0x14010000 0 0x1000>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA2>;
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iommus = <&iommu M4U_PORT_DISP_RDMA2>;
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};
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wdma0: wdma@14011000 {
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compatible = "mediatek,mt8173-disp-wdma";
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reg = <0 0x14011000 0 0x1000>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_WDMA0>;
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iommus = <&iommu M4U_PORT_DISP_WDMA0>;
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};
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wdma1: wdma@14012000 {
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compatible = "mediatek,mt8173-disp-wdma";
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reg = <0 0x14012000 0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_WDMA1>;
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iommus = <&iommu M4U_PORT_DISP_WDMA1>;
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};
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color0: color@14013000 {
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compatible = "mediatek,mt8173-disp-color";
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reg = <0 0x14013000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR0>;
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};
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color1: color@14014000 {
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compatible = "mediatek,mt8173-disp-color";
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reg = <0 0x14014000 0 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR1>;
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};
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aal@14015000 {
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compatible = "mediatek,mt8173-disp-aal";
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reg = <0 0x14015000 0 0x1000>;
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_AAL>;
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};
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gamma@14016000 {
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compatible = "mediatek,mt8173-disp-gamma";
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reg = <0 0x14016000 0 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_GAMMA>;
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};
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ufoe@1401a000 {
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compatible = "mediatek,mt8173-disp-ufoe";
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reg = <0 0x1401a000 0 0x1000>;
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interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_UFOE>;
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};
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dsi0: dsi@1401b000 {
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/* See mediatek,dsi.txt for details */
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};
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dpi0: dpi@1401d000 {
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/* See mediatek,dpi.txt for details */
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};
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mutex: mutex@14020000 {
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compatible = "mediatek,mt8173-disp-mutex";
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reg = <0 0x14020000 0 0x1000>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_MUTEX_32K>;
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};
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od@14023000 {
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compatible = "mediatek,mt8173-disp-od";
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reg = <0 0x14023000 0 0x1000>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_OD>;
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};
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