15 lines
290 B
Plaintext
15 lines
290 B
Plaintext
Microsemi Ocelot reset controller
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The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
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SoC MIPS core.
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Required Properties:
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- compatible: "mscc,ocelot-chip-reset"
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Example:
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reset@1070008 {
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compatible = "mscc,ocelot-chip-reset";
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reg = <0x1070008 0x4>;
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};
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