183 lines
5.8 KiB
Plaintext
183 lines
5.8 KiB
Plaintext
TI Keystone DSP devices
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=======================
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The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
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sub-systems that are used to offload some of the processor-intensive tasks or
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algorithms, for achieving various system level goals.
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These processor sub-systems usually contain additional sub-modules like L1
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and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
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a dedicated local power/sleep controller etc. The DSP processor core in
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Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
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DSP Device Node:
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================
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Each DSP Core sub-system is represented as a single DT node, and should also
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have an alias with the stem 'rproc' defined. Each node has a number of required
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or optional properties that enable the OS running on the host processor (ARM
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CorePac) to perform the device management of the remote processor and to
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communicate with the remote processor.
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Required properties:
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--------------------
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The following are the mandatory properties:
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- compatible: Should be one of the following,
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"ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
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"ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
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"ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
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"ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
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- reg: Should contain an entry for each value in 'reg-names'.
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Each entry should have the memory region's start address
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and the size of the region, the representation matching
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the parent node's '#address-cells' and '#size-cells' values.
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- reg-names: Should contain strings with the following names, each
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representing a specific internal memory region, and
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should be defined in this order,
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"l2sram", "l1pram", "l1dram"
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- ti,syscon-dev: Should be a pair of the phandle to the Keystone Device
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State Control node, and the register offset of the DSP
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boot address register within that node's address space.
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- resets: Should contain the phandle to the reset controller node
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managing the resets for this device, and a reset
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specifier. Please refer to either of the following reset
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bindings for the reset argument specifier as per SoC,
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Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
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for 66AK2HK/66AK2L/66AK2E SoCs or,
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Documentation/devicetree/bindings/reset/ti,sci-reset.txt
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for 66AK2G SoCs
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- interrupts: Should contain an entry for each value in 'interrupt-names'.
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Each entry should have the interrupt source number used by
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the remote processor to the host processor. The values should
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follow the interrupt-specifier format as dictated by the
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'interrupt-parent' node. The purpose of each is as per the
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description in the 'interrupt-names' property.
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- interrupt-names: Should contain strings with the following names, each
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representing a specific interrupt,
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"vring" - interrupt for virtio based IPC
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"exception" - interrupt for exception notification
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- kick-gpios: Should specify the gpio device needed for the virtio IPC
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stack. This will be used to interrupt the remote processor.
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The gpio device to be used is as per the bindings in,
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Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
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SoC-specific Required properties:
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---------------------------------
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The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E
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SoCs only:
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- clocks: Should contain the device's input clock, and should be
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defined as per the bindings in,
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Documentation/devicetree/bindings/clock/keystone-gate.txt
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The following are mandatory properties for Keystone 2 66AK2G SoCs only:
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- power-domains: Should contain a phandle to a PM domain provider node
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and an args specifier containing the DSP device id
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value. This property is as per the binding,
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Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
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Optional properties:
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--------------------
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- memory-region: phandle to the reserved memory node to be associated
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with the remoteproc device. The reserved memory node
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can be a CMA memory node, and should be defined as
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per the bindings in
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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Examples:
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---------
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1.
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/* 66AK2H/K DSP aliases */
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aliases {
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rproc0 = &dsp0;
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rproc1 = &dsp1;
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rproc2 = &dsp2;
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rproc3 = &dsp3;
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rproc4 = &dsp4;
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rproc5 = &dsp5;
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rproc6 = &dsp6;
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rproc7 = &dsp7;
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};
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/* 66AK2H/K DSP memory node */
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dsp_common_memory: dsp-common-memory@81f800000 {
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compatible = "shared-dma-pool";
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reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
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reusable;
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};
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};
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/* 66AK2H/K DSP node */
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soc {
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dsp0: dsp@10800000 {
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compatible = "ti,k2hk-dsp";
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reg = <0x10800000 0x00100000>,
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<0x10e00000 0x00008000>,
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<0x10f00000 0x00008000>;
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reg-names = "l2sram", "l1pram", "l1dram";
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clocks = <&clkgem0>;
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ti,syscon-dev = <&devctrl 0x40>;
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resets = <&pscrst 0>;
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interrupt-parent = <&kirq0>;
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interrupts = <0 8>;
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interrupt-names = "vring", "exception";
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kick-gpios = <&dspgpio0 27 0>;
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memory-region = <&dsp_common_memory>;
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};
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};
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2.
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/* 66AK2G DSP alias */
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aliases {
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rproc0 = &dsp0;
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};
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/* 66AK2G DSP memory node */
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dsp_common_memory: dsp-common-memory@81f800000 {
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compatible = "shared-dma-pool";
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reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
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reusable;
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};
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};
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/* 66AK2G DSP node */
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soc {
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dsp0: dsp@10800000 {
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compatible = "ti,k2g-dsp";
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reg = <0x10800000 0x00100000>,
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<0x10e00000 0x00008000>,
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<0x10f00000 0x00008000>;
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reg-names = "l2sram", "l1pram", "l1dram";
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power-domains = <&k2g_pds 0x0046>;
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ti,syscon-dev = <&devctrl 0x40>;
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resets = <&k2g_reset 0x0046 0x1>;
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interrupt-parent = <&kirq0>;
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interrupts = <0 8>;
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interrupt-names = "vring", "exception";
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kick-gpios = <&dspgpio0 27 0>;
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memory-region = <&dsp_common_memory>;
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};
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};
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