120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
/*
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* Copyright © 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef IOP_ADMA_H
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#define IOP_ADMA_H
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#include <linux/types.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#define IOP_ADMA_SLOT_SIZE 32
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#define IOP_ADMA_THRESHOLD 4
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#ifdef DEBUG
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#define IOP_PARANOIA 1
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#else
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#define IOP_PARANOIA 0
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#endif
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#define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x))
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/**
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* struct iop_adma_device - internal representation of an ADMA device
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* @pdev: Platform device
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* @id: HW ADMA Device selector
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* @dma_desc_pool: base of DMA descriptor region (DMA address)
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* @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
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* @common: embedded struct dma_device
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*/
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struct iop_adma_device {
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struct platform_device *pdev;
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int id;
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dma_addr_t dma_desc_pool;
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void *dma_desc_pool_virt;
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struct dma_device common;
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};
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/**
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* struct iop_adma_chan - internal representation of an ADMA device
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* @pending: allows batching of hardware operations
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* @lock: serializes enqueue/dequeue operations to the slot pool
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* @mmr_base: memory mapped register base
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* @chain: device chain view of the descriptors
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* @device: parent device
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* @common: common dmaengine channel object members
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* @last_used: place holder for allocation to continue from where it left off
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* @all_slots: complete domain of slots usable by the channel
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* @slots_allocated: records the actual size of the descriptor slot pool
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* @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
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*/
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struct iop_adma_chan {
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int pending;
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spinlock_t lock; /* protects the descriptor slot pool */
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void __iomem *mmr_base;
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struct list_head chain;
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struct iop_adma_device *device;
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struct dma_chan common;
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struct iop_adma_desc_slot *last_used;
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struct list_head all_slots;
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int slots_allocated;
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struct tasklet_struct irq_tasklet;
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};
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/**
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* struct iop_adma_desc_slot - IOP-ADMA software descriptor
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* @slot_node: node on the iop_adma_chan.all_slots list
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* @chain_node: node on the op_adma_chan.chain list
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* @hw_desc: virtual address of the hardware descriptor chain
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* @phys: hardware address of the hardware descriptor chain
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* @group_head: first operation in a transaction
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* @slot_cnt: total slots used in an transaction (group of operations)
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* @slots_per_op: number of slots per operation
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* @idx: pool index
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* @tx_list: list of descriptors that are associated with one operation
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* @async_tx: support for the async_tx api
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* @group_list: list of slots that make up a multi-descriptor transaction
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* for example transfer lengths larger than the supported hw max
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* @xor_check_result: result of zero sum
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* @crc32_result: result crc calculation
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*/
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struct iop_adma_desc_slot {
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struct list_head slot_node;
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struct list_head chain_node;
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void *hw_desc;
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struct iop_adma_desc_slot *group_head;
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u16 slot_cnt;
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u16 slots_per_op;
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u16 idx;
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struct list_head tx_list;
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struct dma_async_tx_descriptor async_tx;
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union {
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u32 *xor_check_result;
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u32 *crc32_result;
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u32 *pq_check_result;
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};
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};
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struct iop_adma_platform_data {
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int hw_id;
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dma_cap_mask_t cap_mask;
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size_t pool_size;
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};
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#define to_iop_sw_desc(addr_hw_desc) \
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container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
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#define iop_hw_desc_slot_idx(hw_desc, idx) \
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( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
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#endif
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