84 lines
1.4 KiB
Plaintext
84 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the V3H Starter Kit board
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018 Cogent Embedded, Inc.
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*/
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/dts-v1/;
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#include "r8a77980.dtsi"
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/ {
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model = "Renesas V3H Starter Kit board";
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compatible = "renesas,v3hsk", "renesas,r8a77980";
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aliases {
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serial0 = &scif0;
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ethernet0 = &gether;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0 0x48000000 0 0x78000000>;
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&gether {
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pinctrl-0 = <&gether_pins>;
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pinctrl-names = "default";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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renesas,no-ether-link;
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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interrupt-parent = <&gpio4>;
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interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&pfc {
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gether_pins: gether {
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groups = "gether_mdio_a", "gether_rgmii",
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"gether_txcrefclk", "gether_txcrefclk_mega";
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function = "gether";
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};
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk_b";
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function = "scif_clk";
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};
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <14745600>;
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};
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