393 lines
10 KiB
Plaintext
393 lines
10 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
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*
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* This device tree is pruned and patched by early boot code before
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* use. Because of this, it contains a super-set of the available
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* devices and properties.
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*/
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/include/ "octeon_3xxx.dtsi"
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/ {
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soc@0 {
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smi0: mdio@1180000001800 {
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phy0: ethernet-phy@0 {
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compatible = "marvell,88e1118";
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marvell,reg-init =
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/* Fix rx and tx clock transition timing */
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<2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
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/* Adjust LED drive. */
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<3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
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/* irq, blink-activity, blink-link */
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<3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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compatible = "marvell,88e1118";
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marvell,reg-init =
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/* Fix rx and tx clock transition timing */
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<2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
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/* Adjust LED drive. */
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<3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
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/* irq, blink-activity, blink-link */
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<3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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};
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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};
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phy9: ethernet-phy@9 {
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reg = <9>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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};
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};
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smi1: mdio@1180000001900 {
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compatible = "cavium,octeon-3860-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x11800 0x00001900 0x0 0x40>;
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phy100: ethernet-phy@1 {
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reg = <1>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy101: ethernet-phy@2 {
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reg = <2>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy102: ethernet-phy@3 {
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reg = <3>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy103: ethernet-phy@4 {
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reg = <4>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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};
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mix0: ethernet@1070000100000 {
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compatible = "cavium,octeon-5750-mix";
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reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
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<0x11800 0xE0000000 0x0 0x300>, /* AGL */
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<0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
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<0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
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cell-index = <0>;
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interrupts = <0 62>, <1 46>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy0>;
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};
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mix1: ethernet@1070000100800 {
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compatible = "cavium,octeon-5750-mix";
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reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
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<0x11800 0xE0000800 0x0 0x300>, /* AGL */
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<0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
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<0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
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cell-index = <1>;
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interrupts = <1 18>, < 1 46>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy1>;
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};
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pip: pip@11800a0000000 {
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interface@0 {
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ethernet@0 {
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phy-handle = <&phy2>;
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cavium,alt-phy-handle = <&phy100>;
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};
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ethernet@1 {
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phy-handle = <&phy3>;
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cavium,alt-phy-handle = <&phy101>;
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};
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ethernet@2 {
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phy-handle = <&phy4>;
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cavium,alt-phy-handle = <&phy102>;
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};
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ethernet@3 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x3>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy5>;
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cavium,alt-phy-handle = <&phy103>;
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};
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ethernet@4 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x4>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@5 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x5>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@6 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x6>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@7 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x7>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@8 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x8>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@9 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x9>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@a {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0xa>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@b {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0xb>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@c {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0xc>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@d {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0xd>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@e {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0xe>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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ethernet@f {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0xf>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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};
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interface@1 {
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ethernet@0 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x0>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy6>;
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};
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ethernet@1 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x1>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy7>;
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};
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ethernet@2 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x2>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy8>;
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};
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ethernet@3 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x3>; /* Port */
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-handle = <&phy9>;
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};
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};
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};
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twsi0: i2c@1180000001000 {
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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tmp@4c {
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compatible = "ti,tmp421";
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reg = <0x4c>;
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};
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};
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twsi1: i2c@1180000001200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cavium,octeon-3860-twsi";
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reg = <0x11800 0x00001200 0x0 0x200>;
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interrupts = <0 59>;
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clock-frequency = <100000>;
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};
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uart1: serial@1180000000c00 {
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compatible = "cavium,octeon-3860-uart","ns16550";
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reg = <0x11800 0x00000c00 0x0 0x400>;
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clock-frequency = <0>;
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current-speed = <115200>;
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reg-shift = <3>;
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interrupts = <0 35>;
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};
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uart2: serial@1180000000400 {
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compatible = "cavium,octeon-3860-uart","ns16550";
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reg = <0x11800 0x00000400 0x0 0x400>;
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clock-frequency = <0>;
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current-speed = <115200>;
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reg-shift = <3>;
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interrupts = <1 16>;
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};
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bootbus: bootbus@1180000000000 {
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led0: led-display@4,0 {
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compatible = "avago,hdsp-253x";
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reg = <4 0x20 0x20>, <4 0 0x20>;
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};
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cf0: compact-flash@5,0 {
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compatible = "cavium,ebt3000-compact-flash";
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reg = <5 0 0x10000>, <6 0 0x10000>;
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cavium,bus-width = <16>;
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cavium,true-ide;
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cavium,dma-engine-handle = <&dma0>;
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};
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};
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uctl: uctl@118006f000000 {
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compatible = "cavium,octeon-6335-uctl";
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reg = <0x11800 0x6f000000 0x0 0x100>;
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ranges; /* Direct mapping */
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#address-cells = <2>;
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#size-cells = <2>;
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/* 12MHz, 24MHz and 48MHz allowed */
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refclk-frequency = <12000000>;
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/* Either "crystal" or "external" */
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refclk-type = "crystal";
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ehci@16f0000000000 {
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compatible = "cavium,octeon-6335-ehci","usb-ehci";
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reg = <0x16f00 0x00000000 0x0 0x100>;
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interrupts = <0 56>;
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big-endian-regs;
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};
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ohci@16f0000000400 {
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compatible = "cavium,octeon-6335-ohci","usb-ohci";
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reg = <0x16f00 0x00000400 0x0 0x100>;
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interrupts = <0 56>;
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big-endian-regs;
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};
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};
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usbn: usbn@1180068000000 {
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/* 12MHz, 24MHz and 48MHz allowed */
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refclk-frequency = <12000000>;
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/* Either "crystal" or "external" */
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refclk-type = "crystal";
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};
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};
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aliases {
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mix0 = &mix0;
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mix1 = &mix1;
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pip = &pip;
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smi0 = &smi0;
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smi1 = &smi1;
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twsi0 = &twsi0;
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twsi1 = &twsi1;
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uart0 = &uart0;
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uart1 = &uart1;
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uart2 = &uart2;
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flash0 = &flash0;
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cf0 = &cf0;
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uctl = &uctl;
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usbn = &usbn;
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led0 = &led0;
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};
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};
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