222 lines
5.4 KiB
C
222 lines
5.4 KiB
C
/*
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* Switch a MMU context.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_MMU_CONTEXT_H
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#define _ASM_MMU_CONTEXT_H
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/mm_types.h>
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#include <linux/smp.h>
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#include <linux/slab.h>
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#include <asm/cacheflush.h>
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#include <asm/dsemul.h>
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#include <asm/hazards.h>
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#include <asm/tlbflush.h>
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#include <asm-generic/mm_hooks.h>
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#define htw_set_pwbase(pgd) \
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do { \
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if (cpu_has_htw) { \
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write_c0_pwbase(pgd); \
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back_to_back_c0_hazard(); \
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} \
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} while (0)
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extern void tlbmiss_handler_setup_pgd(unsigned long);
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extern char tlbmiss_handler_setup_pgd_end[];
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/* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */
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#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
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do { \
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tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
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htw_set_pwbase((unsigned long)pgd); \
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} while (0)
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#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
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#define TLBMISS_HANDLER_RESTORE() \
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write_c0_xcontext((unsigned long) smp_processor_id() << \
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SMP_CPUID_REGSHIFT)
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#define TLBMISS_HANDLER_SETUP() \
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do { \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
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TLBMISS_HANDLER_RESTORE(); \
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} while (0)
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#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
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/*
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* For the fast tlb miss handlers, we keep a per cpu array of pointers
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* to the current pgd for each processor. Also, the proc. id is stuffed
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* into the context register.
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*/
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extern unsigned long pgd_current[];
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#define TLBMISS_HANDLER_RESTORE() \
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write_c0_context((unsigned long) smp_processor_id() << \
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SMP_CPUID_REGSHIFT)
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#define TLBMISS_HANDLER_SETUP() \
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TLBMISS_HANDLER_RESTORE(); \
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back_to_back_c0_hazard(); \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
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/*
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* All unused by hardware upper bits will be considered
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* as a software asid extension.
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*/
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static inline u64 asid_version_mask(unsigned int cpu)
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{
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unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
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return ~(u64)(asid_mask | (asid_mask - 1));
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}
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static inline u64 asid_first_version(unsigned int cpu)
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{
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return ~asid_version_mask(cpu) + 1;
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}
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#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
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#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
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#define cpu_asid(cpu, mm) \
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(cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/* Normal, classic MIPS get_new_mmu_context */
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static inline void
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get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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{
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u64 asid = asid_cache(cpu);
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if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) {
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if (cpu_has_vtag_icache)
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flush_icache_all();
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local_flush_tlb_all(); /* start new asid cycle */
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}
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cpu_context(cpu, mm) = asid_cache(cpu) = asid;
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}
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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static inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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int i;
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for_each_possible_cpu(i)
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cpu_context(i, mm) = 0;
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mm->context.bd_emupage_allocmap = NULL;
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spin_lock_init(&mm->context.bd_emupage_lock);
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init_waitqueue_head(&mm->context.bd_emupage_queue);
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return 0;
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long flags;
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local_irq_save(flags);
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htw_stop();
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/* Check if our ASID is of an older version and thus invalid */
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if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu))
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get_new_mmu_context(next, cpu);
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write_c0_entryhi(cpu_asid(cpu, next));
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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/*
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* Mark current->active_mm as not "active" anymore.
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* We don't want to mislead possible IPI tlb flush routines.
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*/
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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htw_start();
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local_irq_restore(flags);
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}
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/*
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* Destroy context related info for an mm_struct that is about
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* to be put to rest.
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*/
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static inline void destroy_context(struct mm_struct *mm)
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{
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dsemul_mm_cleanup(mm);
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}
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#define deactivate_mm(tsk, mm) do { } while (0)
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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static inline void
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activate_mm(struct mm_struct *prev, struct mm_struct *next)
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{
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unsigned long flags;
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unsigned int cpu = smp_processor_id();
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local_irq_save(flags);
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htw_stop();
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/* Unconditionally get a new ASID. */
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get_new_mmu_context(next, cpu);
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write_c0_entryhi(cpu_asid(cpu, next));
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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/* mark mmu ownership change */
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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htw_start();
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local_irq_restore(flags);
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}
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/*
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* If mm is currently active_mm, we can't really drop it. Instead,
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* we will get a new one for it.
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*/
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static inline void
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drop_mmu_context(struct mm_struct *mm, unsigned cpu)
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{
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unsigned long flags;
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local_irq_save(flags);
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htw_stop();
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if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
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get_new_mmu_context(mm, cpu);
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write_c0_entryhi(cpu_asid(cpu, mm));
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} else {
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/* will get a new context next time */
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cpu_context(cpu, mm) = 0;
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}
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htw_start();
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local_irq_restore(flags);
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}
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#endif /* _ASM_MMU_CONTEXT_H */
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