300 lines
9.5 KiB
ArmAsm
300 lines
9.5 KiB
ArmAsm
/*
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* Signal trampolines for 32 bits processes in a ppc64 kernel for
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* use in the vDSO
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*
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* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
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* Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/unistd.h>
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#include <asm/vdso.h>
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.text
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/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from
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the return address to get an address in the middle of the presumed
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call instruction. Since we don't have a call here, we artificially
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extend the range covered by the unwind info by adding a nop before
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the real start. */
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nop
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V_FUNCTION_BEGIN(__kernel_sigtramp32)
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.Lsig_start = . - 4
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li r0,__NR_sigreturn
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sc
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.Lsig_end:
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V_FUNCTION_END(__kernel_sigtramp32)
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.Lsigrt_start:
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nop
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V_FUNCTION_BEGIN(__kernel_sigtramp_rt32)
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li r0,__NR_rt_sigreturn
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sc
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.Lsigrt_end:
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V_FUNCTION_END(__kernel_sigtramp_rt32)
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.section .eh_frame,"a",@progbits
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/* Register r1 can be found at offset 4 of a pt_regs structure.
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A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
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#define cfa_save \
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.byte 0x0f; /* DW_CFA_def_cfa_expression */ \
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.uleb128 9f - 1f; /* length */ \
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1: \
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.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
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.byte 0x06; /* DW_OP_deref */ \
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.byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
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.byte 0x06; /* DW_OP_deref */ \
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9:
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/* Register REGNO can be found at offset OFS of a pt_regs structure.
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A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
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#define rsave(regno, ofs) \
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.byte 0x10; /* DW_CFA_expression */ \
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.uleb128 regno; /* regno */ \
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.uleb128 9f - 1f; /* length */ \
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1: \
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.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
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.byte 0x06; /* DW_OP_deref */ \
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.ifne ofs; \
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.byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
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.endif; \
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9:
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/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
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of the VMX reg struct. The VMX reg struct is at offset VREGS of
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the pt_regs struct. This macro is for REGNO == 0, and contains
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'subroutines' that the other macros jump to. */
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#define vsave_msr0(regno) \
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.byte 0x10; /* DW_CFA_expression */ \
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.uleb128 regno + 77; /* regno */ \
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.uleb128 9f - 1f; /* length */ \
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1: \
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.byte 0x30 + regno; /* DW_OP_lit0 */ \
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2: \
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.byte 0x40; /* DW_OP_lit16 */ \
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.byte 0x1e; /* DW_OP_mul */ \
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3: \
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.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
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.byte 0x06; /* DW_OP_deref */ \
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.byte 0x12; /* DW_OP_dup */ \
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.byte 0x23; /* DW_OP_plus_uconst */ \
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.uleb128 33*RSIZE; /* msr offset */ \
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.byte 0x06; /* DW_OP_deref */ \
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.byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \
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.byte 0x1a; /* DW_OP_and */ \
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.byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \
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.byte 0x30; /* DW_OP_lit0 */ \
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.byte 0x29; /* DW_OP_eq */ \
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.byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \
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.byte 0x13; /* DW_OP_drop, pop the 0 */ \
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.byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
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.byte 0x22; /* DW_OP_plus */ \
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.byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \
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9:
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/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
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of the VMX reg struct. REGNO is 1 thru 31. */
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#define vsave_msr1(regno) \
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.byte 0x10; /* DW_CFA_expression */ \
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.uleb128 regno + 77; /* regno */ \
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.uleb128 9f - 1f; /* length */ \
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1: \
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.byte 0x30 + regno; /* DW_OP_lit n */ \
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.byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
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9:
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/* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
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the VMX save block. */
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#define vsave_msr2(regno, ofs) \
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.byte 0x10; /* DW_CFA_expression */ \
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.uleb128 regno + 77; /* regno */ \
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.uleb128 9f - 1f; /* length */ \
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1: \
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.byte 0x0a; .short ofs; /* DW_OP_const2u */ \
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.byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \
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9:
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/* VMX register REGNO is at offset OFS of the VMX save area. */
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#define vsave(regno, ofs) \
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.byte 0x10; /* DW_CFA_expression */ \
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.uleb128 regno + 77; /* regno */ \
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.uleb128 9f - 1f; /* length */ \
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1: \
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.byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
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.byte 0x06; /* DW_OP_deref */ \
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.byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
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.byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
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9:
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/* This is where the pt_regs pointer can be found on the stack. */
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#define PTREGS 64+28
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/* Size of regs. */
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#define RSIZE 4
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/* This is the offset of the VMX regs. */
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#define VREGS 48*RSIZE+34*8
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/* Describe where general purpose regs are saved. */
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#define EH_FRAME_GEN \
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cfa_save; \
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rsave ( 0, 0*RSIZE); \
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rsave ( 2, 2*RSIZE); \
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rsave ( 3, 3*RSIZE); \
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rsave ( 4, 4*RSIZE); \
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rsave ( 5, 5*RSIZE); \
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rsave ( 6, 6*RSIZE); \
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rsave ( 7, 7*RSIZE); \
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rsave ( 8, 8*RSIZE); \
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rsave ( 9, 9*RSIZE); \
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rsave (10, 10*RSIZE); \
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rsave (11, 11*RSIZE); \
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rsave (12, 12*RSIZE); \
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rsave (13, 13*RSIZE); \
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rsave (14, 14*RSIZE); \
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rsave (15, 15*RSIZE); \
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rsave (16, 16*RSIZE); \
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rsave (17, 17*RSIZE); \
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rsave (18, 18*RSIZE); \
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rsave (19, 19*RSIZE); \
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rsave (20, 20*RSIZE); \
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rsave (21, 21*RSIZE); \
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rsave (22, 22*RSIZE); \
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rsave (23, 23*RSIZE); \
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rsave (24, 24*RSIZE); \
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rsave (25, 25*RSIZE); \
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rsave (26, 26*RSIZE); \
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rsave (27, 27*RSIZE); \
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rsave (28, 28*RSIZE); \
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rsave (29, 29*RSIZE); \
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rsave (30, 30*RSIZE); \
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rsave (31, 31*RSIZE); \
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rsave (67, 32*RSIZE); /* ap, used as temp for nip */ \
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rsave (65, 36*RSIZE); /* lr */ \
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rsave (70, 38*RSIZE) /* cr */
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/* Describe where the FP regs are saved. */
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#define EH_FRAME_FP \
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rsave (32, 48*RSIZE + 0*8); \
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rsave (33, 48*RSIZE + 1*8); \
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rsave (34, 48*RSIZE + 2*8); \
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rsave (35, 48*RSIZE + 3*8); \
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rsave (36, 48*RSIZE + 4*8); \
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rsave (37, 48*RSIZE + 5*8); \
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rsave (38, 48*RSIZE + 6*8); \
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rsave (39, 48*RSIZE + 7*8); \
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rsave (40, 48*RSIZE + 8*8); \
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rsave (41, 48*RSIZE + 9*8); \
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rsave (42, 48*RSIZE + 10*8); \
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rsave (43, 48*RSIZE + 11*8); \
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rsave (44, 48*RSIZE + 12*8); \
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rsave (45, 48*RSIZE + 13*8); \
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rsave (46, 48*RSIZE + 14*8); \
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rsave (47, 48*RSIZE + 15*8); \
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rsave (48, 48*RSIZE + 16*8); \
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rsave (49, 48*RSIZE + 17*8); \
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rsave (50, 48*RSIZE + 18*8); \
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rsave (51, 48*RSIZE + 19*8); \
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rsave (52, 48*RSIZE + 20*8); \
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rsave (53, 48*RSIZE + 21*8); \
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rsave (54, 48*RSIZE + 22*8); \
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rsave (55, 48*RSIZE + 23*8); \
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rsave (56, 48*RSIZE + 24*8); \
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rsave (57, 48*RSIZE + 25*8); \
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rsave (58, 48*RSIZE + 26*8); \
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rsave (59, 48*RSIZE + 27*8); \
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rsave (60, 48*RSIZE + 28*8); \
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rsave (61, 48*RSIZE + 29*8); \
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rsave (62, 48*RSIZE + 30*8); \
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rsave (63, 48*RSIZE + 31*8)
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/* Describe where the VMX regs are saved. */
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#ifdef CONFIG_ALTIVEC
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#define EH_FRAME_VMX \
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vsave_msr0 ( 0); \
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vsave_msr1 ( 1); \
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vsave_msr1 ( 2); \
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vsave_msr1 ( 3); \
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vsave_msr1 ( 4); \
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vsave_msr1 ( 5); \
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vsave_msr1 ( 6); \
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vsave_msr1 ( 7); \
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vsave_msr1 ( 8); \
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vsave_msr1 ( 9); \
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vsave_msr1 (10); \
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vsave_msr1 (11); \
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vsave_msr1 (12); \
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vsave_msr1 (13); \
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vsave_msr1 (14); \
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vsave_msr1 (15); \
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vsave_msr1 (16); \
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vsave_msr1 (17); \
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vsave_msr1 (18); \
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vsave_msr1 (19); \
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vsave_msr1 (20); \
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vsave_msr1 (21); \
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vsave_msr1 (22); \
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vsave_msr1 (23); \
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vsave_msr1 (24); \
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vsave_msr1 (25); \
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vsave_msr1 (26); \
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vsave_msr1 (27); \
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vsave_msr1 (28); \
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vsave_msr1 (29); \
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vsave_msr1 (30); \
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vsave_msr1 (31); \
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vsave_msr2 (33, 32*16+12); \
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vsave (32, 32*16)
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#else
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#define EH_FRAME_VMX
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#endif
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.Lcie:
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.long .Lcie_end - .Lcie_start
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.Lcie_start:
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.long 0 /* CIE ID */
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.byte 1 /* Version number */
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.string "zRS" /* NUL-terminated augmentation string */
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.uleb128 4 /* Code alignment factor */
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.sleb128 -4 /* Data alignment factor */
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.byte 67 /* Return address register column, ap */
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.uleb128 1 /* Augmentation value length */
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.byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
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.byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */
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.balign 4
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.Lcie_end:
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.long .Lfde0_end - .Lfde0_start
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.Lfde0_start:
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.long .Lfde0_start - .Lcie /* CIE pointer. */
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.long .Lsig_start - . /* PC start, length */
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.long .Lsig_end - .Lsig_start
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.uleb128 0 /* Augmentation */
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EH_FRAME_GEN
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EH_FRAME_FP
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EH_FRAME_VMX
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.balign 4
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.Lfde0_end:
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/* We have a different stack layout for rt_sigreturn. */
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#undef PTREGS
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#define PTREGS 64+16+128+20+28
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.long .Lfde1_end - .Lfde1_start
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.Lfde1_start:
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.long .Lfde1_start - .Lcie /* CIE pointer. */
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.long .Lsigrt_start - . /* PC start, length */
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.long .Lsigrt_end - .Lsigrt_start
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.uleb128 0 /* Augmentation */
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EH_FRAME_GEN
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EH_FRAME_FP
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EH_FRAME_VMX
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.balign 4
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.Lfde1_end:
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