94 lines
2 KiB
C
94 lines
2 KiB
C
/*
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* arch/sh/mm/tlb-urb.c
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*
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* TLB entry wiring helpers for URB-equipped parts.
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*
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* Copyright (C) 2010 Matt Fleming
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <asm/tlb.h>
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#include <asm/mmu_context.h>
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/*
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* Load the entry for 'addr' into the TLB and wire the entry.
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*/
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void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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{
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unsigned long status, flags;
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int urb;
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local_irq_save(flags);
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status = __raw_readl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URC;
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/*
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* Make sure we're not trying to wire the last TLB entry slot.
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*/
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BUG_ON(!--urb);
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urb = urb % MMUCR_URB_NENTRIES;
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/*
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* Insert this entry into the highest non-wired TLB slot (via
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* the URC field).
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*/
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status |= (urb << MMUCR_URC_SHIFT);
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__raw_writel(status, MMUCR);
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ctrl_barrier();
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/* Load the entry into the TLB */
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__update_tlb(vma, addr, pte);
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/* ... and wire it up. */
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status = __raw_readl(MMUCR);
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status &= ~MMUCR_URB;
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status |= (urb << MMUCR_URB_SHIFT);
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__raw_writel(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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/*
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* Unwire the last wired TLB entry.
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*
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* It should also be noted that it is not possible to wire and unwire
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* TLB entries in an arbitrary order. If you wire TLB entry N, followed
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* by entry N+1, you must unwire entry N+1 first, then entry N. In this
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* respect, it works like a stack or LIFO queue.
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*/
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void tlb_unwire_entry(void)
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{
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unsigned long status, flags;
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int urb;
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local_irq_save(flags);
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status = __raw_readl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URB;
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/*
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* Make sure we're not trying to unwire a TLB entry when none
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* have been wired.
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*/
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BUG_ON(urb++ == MMUCR_URB_NENTRIES);
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urb = urb % MMUCR_URB_NENTRIES;
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status |= (urb << MMUCR_URB_SHIFT);
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__raw_writel(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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