193 lines
5.4 KiB
C
193 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SPARC64_MMU_CONTEXT_H
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#define __SPARC64_MMU_CONTEXT_H
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/* Derived heavily from Linus's Alpha/AXP ASN code... */
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#ifndef __ASSEMBLY__
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#include <linux/spinlock.h>
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#include <linux/mm_types.h>
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#include <linux/smp.h>
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#include <linux/sched.h>
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#include <asm/spitfire.h>
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#include <asm/adi_64.h>
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#include <asm-generic/mm_hooks.h>
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#include <asm/percpu.h>
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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extern spinlock_t ctx_alloc_lock;
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extern unsigned long tlb_context_cache;
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extern unsigned long mmu_context_bmap[];
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DECLARE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm);
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void get_new_mmu_context(struct mm_struct *mm);
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int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void destroy_context(struct mm_struct *mm);
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void __tsb_context_switch(unsigned long pgd_pa,
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struct tsb_config *tsb_base,
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struct tsb_config *tsb_huge,
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unsigned long tsb_descr_pa,
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unsigned long secondary_ctx);
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static inline void tsb_context_switch_ctx(struct mm_struct *mm,
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unsigned long ctx)
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{
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__tsb_context_switch(__pa(mm->pgd),
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&mm->context.tsb_block[MM_TSB_BASE],
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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(mm->context.tsb_block[MM_TSB_HUGE].tsb ?
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&mm->context.tsb_block[MM_TSB_HUGE] :
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NULL)
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#else
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NULL
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#endif
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, __pa(&mm->context.tsb_descr[MM_TSB_BASE]),
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ctx);
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}
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#define tsb_context_switch(X) tsb_context_switch_ctx(X, 0)
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void tsb_grow(struct mm_struct *mm,
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unsigned long tsb_index,
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unsigned long mm_rss);
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#ifdef CONFIG_SMP
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void smp_tsb_sync(struct mm_struct *mm);
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#else
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#define smp_tsb_sync(__mm) do { } while (0)
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#endif
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/* Set MMU context in the actual hardware. */
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#define load_secondary_context(__mm) \
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__asm__ __volatile__( \
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"\n661: stxa %0, [%1] %2\n" \
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" .section .sun4v_1insn_patch, \"ax\"\n" \
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" .word 661b\n" \
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" stxa %0, [%1] %3\n" \
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" .previous\n" \
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" flush %%g6\n" \
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: /* No outputs */ \
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: "r" (CTX_HWBITS((__mm)->context)), \
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"r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
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void __flush_tlb_mm(unsigned long, unsigned long);
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/* Switch the current MM context. */
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static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
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{
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unsigned long ctx_valid, flags;
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int cpu = smp_processor_id();
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per_cpu(per_cpu_secondary_mm, cpu) = mm;
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if (unlikely(mm == &init_mm))
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return;
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spin_lock_irqsave(&mm->context.lock, flags);
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ctx_valid = CTX_VALID(mm->context);
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if (!ctx_valid)
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get_new_mmu_context(mm);
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/* We have to be extremely careful here or else we will miss
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* a TSB grow if we switch back and forth between a kernel
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* thread and an address space which has it's TSB size increased
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* on another processor.
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*
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* It is possible to play some games in order to optimize the
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* switch, but the safest thing to do is to unconditionally
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* perform the secondary context load and the TSB context switch.
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*
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* For reference the bad case is, for address space "A":
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*
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* CPU 0 CPU 1
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* run address space A
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* set cpu0's bits in cpu_vm_mask
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* switch to kernel thread, borrow
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* address space A via entry_lazy_tlb
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* run address space A
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* set cpu1's bit in cpu_vm_mask
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* flush_tlb_pending()
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* reset cpu_vm_mask to just cpu1
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* TSB grow
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* run address space A
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* context was valid, so skip
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* TSB context switch
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*
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* At that point cpu0 continues to use a stale TSB, the one from
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* before the TSB grow performed on cpu1. cpu1 did not cross-call
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* cpu0 to update it's TSB because at that point the cpu_vm_mask
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* only had cpu1 set in it.
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*/
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tsb_context_switch_ctx(mm, CTX_HWBITS(mm->context));
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/* Any time a processor runs a context on an address space
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* for the first time, we must flush that context out of the
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* local TLB.
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*/
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if (!ctx_valid || !cpumask_test_cpu(cpu, mm_cpumask(mm))) {
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cpumask_set_cpu(cpu, mm_cpumask(mm));
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__flush_tlb_mm(CTX_HWBITS(mm->context),
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SECONDARY_CONTEXT);
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}
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spin_unlock_irqrestore(&mm->context.lock, flags);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL)
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#define __HAVE_ARCH_START_CONTEXT_SWITCH
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static inline void arch_start_context_switch(struct task_struct *prev)
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{
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/* Save the current state of MCDPER register for the process
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* we are switching from
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*/
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if (adi_capable()) {
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register unsigned long tmp_mcdper;
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__asm__ __volatile__(
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".word 0x83438000\n\t" /* rd %mcdper, %g1 */
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"mov %%g1, %0\n\t"
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: "=r" (tmp_mcdper)
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:
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: "g1");
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if (tmp_mcdper)
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set_tsk_thread_flag(prev, TIF_MCDPER);
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else
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clear_tsk_thread_flag(prev, TIF_MCDPER);
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}
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}
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#define finish_arch_post_lock_switch finish_arch_post_lock_switch
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static inline void finish_arch_post_lock_switch(void)
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{
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/* Restore the state of MCDPER register for the new process
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* just switched to.
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*/
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if (adi_capable()) {
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register unsigned long tmp_mcdper;
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tmp_mcdper = test_thread_flag(TIF_MCDPER);
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__asm__ __volatile__(
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"mov %0, %%g1\n\t"
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".word 0x9d800001\n\t" /* wr %g0, %g1, %mcdper" */
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".word 0xaf902001\n\t" /* wrpr %g0, 1, %pmcdper */
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:
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: "ir" (tmp_mcdper)
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: "g1");
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if (current && current->mm && current->mm->context.adi) {
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struct pt_regs *regs;
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regs = task_pt_regs(current);
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regs->tstate |= TSTATE_MCDE;
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}
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}
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}
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__SPARC64_MMU_CONTEXT_H) */
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