675 lines
17 KiB
C
675 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/fb.h>
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#include <linux/notifier.h>
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#include <linux/string.h>
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#include <mtk_dramc.h>
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#include <mt-plat/upmu_common.h>
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//#include <ext_wd_drv.h>
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#include <mt_emi_api.h>
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#include <mt-plat/mtk_devinfo.h>
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#include <helio-dvfsrc_v2.h>
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#include <helio-dvfsrc-opp.h>
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#include <mtk_dvfsrc_reg.h>
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#include <mtk_spm_internal.h>
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#include <spm/mtk_vcore_dvfs.h>
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#include <mtk_gpufreq.h>
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#include "mmdvfs_pmqos.h"
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__weak unsigned int get_dram_data_rate(void) { return 0; }
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static struct reg_config dvfsrc_init_configs[][128] = {
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/* SPMFW_LP4X_2CH_3600 */
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{
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{ DVFSRC_EMI_REQUEST, 0x00240009 },
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{ DVFSRC_EMI_REQUEST3, 0x09000000 },
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{ DVFSRC_EMI_HRT, 0x003E362C },
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{ DVFSRC_EMI_QOS0, 0x00000033 },
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{ DVFSRC_EMI_QOS1, 0x0000004C },
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{ DVFSRC_EMI_MD2SPM0, 0x0000003F },
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{ DVFSRC_EMI_MD2SPM1, 0x00000000 },
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{ DVFSRC_EMI_MD2SPM2, 0x000080C0 },
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{ DVFSRC_EMI_MD2SPM0_T, 0x00000007 },
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{ DVFSRC_EMI_MD2SPM1_T, 0x00000038 },
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{ DVFSRC_EMI_MD2SPM2_T, 0x000080C0 },
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{ DVFSRC_VCORE_HRT, 0x00000036 },
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{ DVFSRC_MD_SW_CONTROL, 0x20000000 },
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{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000014 },
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{ DVFSRC_INT_EN, 0x00000003 },
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{ DVFSRC_LEVEL_LABEL_0_1, 0x00010000 },
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{ DVFSRC_LEVEL_LABEL_2_3, 0x00020101 },
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{ DVFSRC_LEVEL_LABEL_4_5, 0x01020012 },
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{ DVFSRC_LEVEL_LABEL_6_7, 0x02120112 },
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{ DVFSRC_LEVEL_LABEL_8_9, 0x00230013 },
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{ DVFSRC_LEVEL_LABEL_10_11, 0x01230113 },
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{ DVFSRC_LEVEL_LABEL_12_13, 0x02230213 },
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{ DVFSRC_LEVEL_LABEL_14_15, 0x03230323 },
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{ DVFSRC_FORCE, 0x40000000 },
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{ DVFSRC_RSRV_1, 0x0000000C },
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{ DVFSRC_QOS_EN, 0x0000407F },
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{ DVFSRC_BASIC_CONTROL, 0x0000407B },
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{ DVFSRC_BASIC_CONTROL, 0x0000017B },
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{ DVFSRC_FORCE, 0x00000000 },
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{ -1, 0 },
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},
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/* SPMFW_LP3_1CH_1866 */
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{
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{ DVFSRC_EMI_REQUEST, 0x00240009 },
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{ DVFSRC_EMI_REQUEST3, 0x09000000 },
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{ DVFSRC_EMI_HRT, 0x00000020 },
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{ DVFSRC_EMI_QOS0, 0x00000026 },
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{ DVFSRC_EMI_QOS1, 0x00000033 },
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{ DVFSRC_EMI_MD2SPM0, 0x0000003F },
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{ DVFSRC_EMI_MD2SPM1, 0x00000000 },
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{ DVFSRC_EMI_MD2SPM2, 0x000080C0 },
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{ DVFSRC_EMI_MD2SPM0_T, 0x00000007 },
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{ DVFSRC_EMI_MD2SPM1_T, 0x00000038 },
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{ DVFSRC_EMI_MD2SPM2_T, 0x000080C0 },
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{ DVFSRC_VCORE_HRT, 0x00000020 },
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{ DVFSRC_MD_SW_CONTROL, 0x20000000 },
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{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000014 },
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{ DVFSRC_INT_EN, 0x00000003 },
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{ DVFSRC_LEVEL_LABEL_0_1, 0x00010000 },
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{ DVFSRC_LEVEL_LABEL_2_3, 0x00020101 },
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{ DVFSRC_LEVEL_LABEL_4_5, 0x01020012 },
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{ DVFSRC_LEVEL_LABEL_6_7, 0x02120112 },
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{ DVFSRC_LEVEL_LABEL_8_9, 0x00230013 },
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{ DVFSRC_LEVEL_LABEL_10_11, 0x01230113 },
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{ DVFSRC_LEVEL_LABEL_12_13, 0x02230213 },
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{ DVFSRC_LEVEL_LABEL_14_15, 0x03230323 },
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{ DVFSRC_FORCE, 0x40000000 },
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{ DVFSRC_RSRV_1, 0x0000000C },
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{ DVFSRC_QOS_EN, 0x0000407F },
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{ DVFSRC_BASIC_CONTROL, 0x0000407B },
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{ DVFSRC_BASIC_CONTROL, 0x0000017B },
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{ DVFSRC_FORCE, 0x00000000 },
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{ -1, 0 },
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},
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/* NULL */
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{
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{ -1, 0 },
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},
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};
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struct reg_config *dvfsrc_get_init_conf(void)
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{
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int spmfw_idx = spm_get_spmfw_idx();
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if (spmfw_idx < 0)
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spmfw_idx = ARRAY_SIZE(dvfsrc_init_configs) - 1;
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if (spmfw_idx == SPMFW_LP3_1CH_1866)
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spmfw_idx = 1;
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else
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spmfw_idx = 0;
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pr_info("dvfsrc init config index %d\n", spmfw_idx);
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return dvfsrc_init_configs[spmfw_idx];
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}
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void dvfsrc_update_md_scenario(bool blank)
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{
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switch (spm_get_spmfw_idx()) {
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case SPMFW_LP4X_2CH_3600:
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case SPMFW_LP4X_2CH_3200:
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case SPMFW_LP4_2CH_3200:
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if (blank) {
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dvfsrc_write(DVFSRC_EMI_MD2SPM0_T, 0x0000003F);
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dvfsrc_write(DVFSRC_EMI_MD2SPM1_T, 0x00000000);
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} else {
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dvfsrc_write(DVFSRC_EMI_MD2SPM0_T, 0x00000007);
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dvfsrc_write(DVFSRC_EMI_MD2SPM1_T, 0x00000038);
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}
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break;
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case SPMFW_LP3_1CH_1866:
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if (blank) {
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dvfsrc_write(DVFSRC_EMI_MD2SPM0_T, 0x0000003F);
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dvfsrc_write(DVFSRC_EMI_MD2SPM1_T, 0x00000000);
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} else {
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dvfsrc_write(DVFSRC_EMI_MD2SPM0_T, 0x00000007);
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dvfsrc_write(DVFSRC_EMI_MD2SPM1_T, 0x00000038);
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}
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break;
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default:
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break;
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}
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}
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static int dvfsrc_fb_notifier_call(struct notifier_block *self,
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unsigned long event, void *data)
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{
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struct fb_event *evdata = data;
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int blank;
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if (event != FB_EVENT_BLANK)
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return 0;
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blank = *(int *)evdata->data;
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switch (blank) {
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case FB_BLANK_UNBLANK:
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dvfsrc_update_md_scenario(false);
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break;
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case FB_BLANK_POWERDOWN:
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dvfsrc_update_md_scenario(true);
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break;
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default:
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break;
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}
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return 0;
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}
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static struct notifier_block dvfsrc_fb_notifier = {
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.notifier_call = dvfsrc_fb_notifier_call,
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};
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#if 1
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static int is_bypass_flavor(void)
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{
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int r = 0;
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#if defined(CONFIG_ARM64) && \
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defined(CONFIG_BUILD_ARM64_DTB_OVERLAY_IMAGE_NAMES)
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if (strstr(CONFIG_BUILD_ARM64_DTB_OVERLAY_IMAGE_NAMES,
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"k68v1_64_vcore_dvfs_fix") != NULL)
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r = 0;
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pr_info("flavor check: %s, is_bypass: %d\n",
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CONFIG_BUILD_ARM64_DTB_OVERLAY_IMAGE_NAMES, r);
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#endif
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return r;
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}
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#endif
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static int can_dvfsrc_enable(void)
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{
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int enable = 0;
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#if 1
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if (is_bypass_flavor()) {
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enable = 0;
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pr_info("VCORE DVFS disable for special flavor\n");
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} else {
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enable = 1;
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pr_info("VCORE DVFS enable default\n");
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}
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#endif
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return enable;
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}
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__weak int mtk_rgu_cfg_dvfsrc(int enable) { return 0; }
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__weak int emmc_autok(void)
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{
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pr_info("NOT SUPPORT EMMC AUTOK\n");
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return 0;
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}
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__weak int sd_autok(void)
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{
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pr_info("NOT SUPPORT SD AUTOK\n");
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return 0;
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}
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__weak int sdio_autok(void)
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{
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pr_info("NOT SUPPORT SDIO AUTOK\n");
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return 0;
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}
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void begin_autok_task(void)
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{
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/* notify MM DVFS for msdc autok start */
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mmdvfs_prepare_action(MMDVFS_PREPARE_CALIBRATION_START);
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#if 0 /* def CONFIG_MTK_GPU_SUPPORT */
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/* notify GPU DVFS for msdc autok start */
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mt_gpufreq_disable_by_ptpod();
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#endif
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}
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void finish_autok_task(void)
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{
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/* check if dvfs force is released */
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int force = mtk_pm_qos_request(MTK_PM_QOS_VCORE_DVFS_FORCE_OPP);
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/* notify MM DVFS for msdc autok finish */
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mmdvfs_prepare_action(MMDVFS_PREPARE_CALIBRATION_END);
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#if 0 /* def CONFIG_MTK_GPU_SUPPORT */
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/* notify GPU DVFS for msdc autok finish */
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mt_gpufreq_enable_by_ptpod();
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#endif
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if (force >= 0 && force < 16)
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pr_info("autok task not release force opp: %d\n", force);
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}
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void dvfsrc_autok_manager(void)
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{
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int r = 0;
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begin_autok_task();
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r = emmc_autok();
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pr_info("EMMC autok done: %s\n", (r == 0) ? "Yes" : "No");
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r = sd_autok();
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pr_info("SD autok done: %s\n", (r == 0) ? "Yes" : "No");
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r = sdio_autok();
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pr_info("SDIO autok done: %s\n", (r == 0) ? "Yes" : "No");
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finish_autok_task();
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}
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int helio_dvfsrc_platform_init(struct helio_dvfsrc *dvfsrc)
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{
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mtk_rgu_cfg_dvfsrc(1);
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helio_dvfsrc_sram_reg_init();
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if (can_dvfsrc_enable())
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helio_dvfsrc_enable(1);
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else
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helio_dvfsrc_enable(0);
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dvfsrc->init_config = dvfsrc_get_init_conf();
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helio_dvfsrc_reg_config(dvfsrc->init_config);
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dvfsrc_autok_manager();
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return fb_register_client(&dvfsrc_fb_notifier);
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}
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void get_opp_info(char *p)
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{
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#if defined(CONFIG_MTK_PMIC_COMMON)
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int pmic_val = pmic_get_register_value(PMIC_VCORE_ADDR);
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int vcore_uv = vcore_pmic_to_uv(pmic_val);
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#endif
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int ddr_khz = get_dram_data_rate() * 1000;
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#if defined(CONFIG_MTK_PMIC_COMMON)
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p += sprintf(p, "%-24s: %-8u uv (PMIC: 0x%x)\n",
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"Vcore", vcore_uv, vcore_uv_to_pmic(vcore_uv));
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#endif
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p += sprintf(p, "%-24s: %-8u khz\n", "DDR", ddr_khz);
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p += sprintf(p, "%-24s: %-8u\n", "SW REQ OPP", get_sw_req_vcore_opp());
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}
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void get_dvfsrc_reg(char *p)
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{
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_BASIC_CONTROL",
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dvfsrc_read(DVFSRC_BASIC_CONTROL));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x\n",
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"DVFSRC_SW_REQ(2)",
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dvfsrc_read(DVFSRC_SW_REQ),
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dvfsrc_read(DVFSRC_SW_REQ2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_EMI_QOS0(1)(2)",
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dvfsrc_read(DVFSRC_EMI_QOS0),
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dvfsrc_read(DVFSRC_EMI_QOS1),
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dvfsrc_read(DVFSRC_EMI_QOS2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_EMI_REQUEST(2)(3)",
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dvfsrc_read(DVFSRC_EMI_REQUEST),
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dvfsrc_read(DVFSRC_EMI_REQUEST2),
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dvfsrc_read(DVFSRC_EMI_REQUEST3));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_EMI_MD2SPM0~2",
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dvfsrc_read(DVFSRC_EMI_MD2SPM0),
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dvfsrc_read(DVFSRC_EMI_MD2SPM1),
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dvfsrc_read(DVFSRC_EMI_MD2SPM2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_EMI_MD2SPM0~2_T",
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dvfsrc_read(DVFSRC_EMI_MD2SPM0_T),
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dvfsrc_read(DVFSRC_EMI_MD2SPM1_T),
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dvfsrc_read(DVFSRC_EMI_MD2SPM2_T));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x\n",
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"DVFSRC_VCORE_REQUEST(2)",
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dvfsrc_read(DVFSRC_VCORE_REQUEST),
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dvfsrc_read(DVFSRC_VCORE_REQUEST2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_VCORE_MD2SPM0~2",
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dvfsrc_read(DVFSRC_VCORE_MD2SPM0),
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dvfsrc_read(DVFSRC_VCORE_MD2SPM1),
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dvfsrc_read(DVFSRC_VCORE_MD2SPM2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_VCORE_MD2SPM0~2_T",
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dvfsrc_read(DVFSRC_VCORE_MD2SPM0_T),
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dvfsrc_read(DVFSRC_VCORE_MD2SPM1_T),
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dvfsrc_read(DVFSRC_VCORE_MD2SPM2_T));
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_MD_REQUEST",
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dvfsrc_read(DVFSRC_MD_REQUEST));
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_INT",
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dvfsrc_read(DVFSRC_INT));
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_INT_EN",
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dvfsrc_read(DVFSRC_INT_EN));
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_LEVEL",
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dvfsrc_read(DVFSRC_LEVEL));
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p += sprintf(p, "%-24s: %d, %d, %d, %d, %d\n",
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"DVFSRC_SW_BW_0~4",
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dvfsrc_read(DVFSRC_SW_BW_0),
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dvfsrc_read(DVFSRC_SW_BW_1),
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dvfsrc_read(DVFSRC_SW_BW_2),
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dvfsrc_read(DVFSRC_SW_BW_3),
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dvfsrc_read(DVFSRC_SW_BW_4));
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}
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void get_dvfsrc_record(char *p)
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{
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_FORCE",
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dvfsrc_read(DVFSRC_FORCE));
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_SEC_SW_REQ",
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dvfsrc_read(DVFSRC_SEC_SW_REQ));
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_LAST",
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dvfsrc_read(DVFSRC_LAST));
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p += sprintf(p, "%-24s: 0x%08x\n",
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"DVFSRC_MD_SCENARIO",
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dvfsrc_read(DVFSRC_MD_SCENARIO));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_RECORD_0_0~0_2",
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dvfsrc_read(DVFSRC_RECORD_0_0),
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dvfsrc_read(DVFSRC_RECORD_0_1),
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dvfsrc_read(DVFSRC_RECORD_0_2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_RECORD_1_0~1_2",
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dvfsrc_read(DVFSRC_RECORD_1_0),
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dvfsrc_read(DVFSRC_RECORD_1_1),
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dvfsrc_read(DVFSRC_RECORD_1_2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_RECORD_2_0~2_2",
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dvfsrc_read(DVFSRC_RECORD_2_0),
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dvfsrc_read(DVFSRC_RECORD_2_1),
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dvfsrc_read(DVFSRC_RECORD_2_2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_RECORD_3_0~3_2",
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dvfsrc_read(DVFSRC_RECORD_3_0),
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dvfsrc_read(DVFSRC_RECORD_3_1),
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dvfsrc_read(DVFSRC_RECORD_3_2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
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"DVFSRC_RECORD_4_0~4_2",
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dvfsrc_read(DVFSRC_RECORD_4_0),
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dvfsrc_read(DVFSRC_RECORD_4_1),
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dvfsrc_read(DVFSRC_RECORD_4_2));
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p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
|
|
"DVFSRC_RECORD_5_0~5_2",
|
|
dvfsrc_read(DVFSRC_RECORD_5_0),
|
|
dvfsrc_read(DVFSRC_RECORD_5_1),
|
|
dvfsrc_read(DVFSRC_RECORD_5_2));
|
|
p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
|
|
"DVFSRC_RECORD_6_0~6_2",
|
|
dvfsrc_read(DVFSRC_RECORD_6_0),
|
|
dvfsrc_read(DVFSRC_RECORD_6_1),
|
|
dvfsrc_read(DVFSRC_RECORD_6_2));
|
|
p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x\n",
|
|
"DVFSRC_RECORD_7_0~7_2",
|
|
dvfsrc_read(DVFSRC_RECORD_7_0),
|
|
dvfsrc_read(DVFSRC_RECORD_7_1),
|
|
dvfsrc_read(DVFSRC_RECORD_7_2));
|
|
p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
|
|
"DVFSRC_RECORD_MD_0~3",
|
|
dvfsrc_read(DVFSRC_RECORD_MD_0),
|
|
dvfsrc_read(DVFSRC_RECORD_MD_1),
|
|
dvfsrc_read(DVFSRC_RECORD_MD_2),
|
|
dvfsrc_read(DVFSRC_RECORD_MD_3));
|
|
p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
|
|
"DVFSRC_RECORD_MD_4~7",
|
|
dvfsrc_read(DVFSRC_RECORD_MD_4),
|
|
dvfsrc_read(DVFSRC_RECORD_MD_5),
|
|
dvfsrc_read(DVFSRC_RECORD_MD_6),
|
|
dvfsrc_read(DVFSRC_RECORD_MD_7));
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"DVFSRC_RECORD_COUNT",
|
|
dvfsrc_read(DVFSRC_RECORD_COUNT));
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"DVFSRC_RSRV_0",
|
|
dvfsrc_read(DVFSRC_RSRV_0));
|
|
}
|
|
|
|
/* met profile table */
|
|
unsigned int met_vcorefs_info[INFO_MAX];
|
|
unsigned int met_vcorefs_src[SRC_MAX];
|
|
|
|
char *met_info_name[INFO_MAX] = {
|
|
"OPP",
|
|
"FREQ",
|
|
"VCORE",
|
|
"x__SPM_LEVEL",
|
|
};
|
|
|
|
char *met_src_name[SRC_MAX] = {
|
|
"MD2SPM",
|
|
"SRC_DDR_OPP",
|
|
"DDR__SW_REQ1_PMQOS",
|
|
"DDR__SW_REQ2_CM",
|
|
"DDR__EMI_TOTAL",
|
|
"DDR__QOS_BW",
|
|
"SRC_VCORE_OPP",
|
|
"VCORE__SW_REQ1_PMQOS",
|
|
"VCORE__SW_REQ2_CM",
|
|
"VCORE__SCP",
|
|
"TOTAL_EMI_BW",
|
|
"PMQOS_TOTAL",
|
|
"PMQOS_BW0",
|
|
"PMQOS_BW1",
|
|
"PMQOS_BW2",
|
|
"PMQOS_BW3",
|
|
"PMQOS_BW4",
|
|
"MD_REQ_OPP",
|
|
"BWMON__TOTAL_BW",
|
|
"BWMON__CPU_BW",
|
|
"BWMON__GPU_BW",
|
|
"BWMON__MM_BW",
|
|
};
|
|
|
|
/* met profile function */
|
|
int vcorefs_get_num_opp(void)
|
|
{
|
|
return VCORE_DVFS_OPP_NUM;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_num_opp);
|
|
|
|
int vcorefs_get_opp_info_num(void)
|
|
{
|
|
return INFO_MAX;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_opp_info_num);
|
|
|
|
int vcorefs_get_src_req_num(void)
|
|
{
|
|
return SRC_MAX;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_src_req_num);
|
|
|
|
char **vcorefs_get_opp_info_name(void)
|
|
{
|
|
return met_info_name;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_opp_info_name);
|
|
|
|
char **vcorefs_get_src_req_name(void)
|
|
{
|
|
return met_src_name;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_src_req_name);
|
|
|
|
unsigned int *vcorefs_get_opp_info(void)
|
|
{
|
|
met_vcorefs_info[INFO_OPP_IDX] = get_cur_vcore_dvfs_opp();
|
|
met_vcorefs_info[INFO_FREQ_IDX] = get_cur_ddr_khz();
|
|
met_vcorefs_info[INFO_VCORE_IDX] = get_cur_vcore_uv();
|
|
met_vcorefs_info[INFO_SPM_LEVEL_IDX] = spm_get_dvfs_level();
|
|
|
|
return met_vcorefs_info;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_opp_info);
|
|
|
|
unsigned int *vcorefs_get_src_req(void)
|
|
{
|
|
unsigned int qos_total_bw = dvfsrc_read(DVFSRC_SW_BW_0) +
|
|
dvfsrc_read(DVFSRC_SW_BW_1) +
|
|
dvfsrc_read(DVFSRC_SW_BW_2) +
|
|
dvfsrc_read(DVFSRC_SW_BW_3) +
|
|
dvfsrc_read(DVFSRC_SW_BW_4);
|
|
unsigned int sw_req = dvfsrc_read(DVFSRC_SW_REQ);
|
|
unsigned int sw_req2 = dvfsrc_read(DVFSRC_SW_REQ2);
|
|
unsigned int total_bw_status = get_emi_bwst(0);
|
|
unsigned int total_bw_last = (get_emi_bwvl(0) & 0x7F) * 813;
|
|
unsigned int qos0_thres = dvfsrc_read(DVFSRC_EMI_QOS0);
|
|
unsigned int qos1_thres = dvfsrc_read(DVFSRC_EMI_QOS1);
|
|
|
|
met_vcorefs_src[SRC_MD2SPM_IDX] =
|
|
spm_vcorefs_get_MD_status();
|
|
|
|
met_vcorefs_src[DDR_OPP_IDX] = get_cur_ddr_opp();
|
|
|
|
met_vcorefs_src[DDR_SW_REQ1_PMQOS_IDX] =
|
|
(sw_req >> EMI_SW_AP_SHIFT) & EMI_SW_AP_MASK;
|
|
|
|
met_vcorefs_src[DDR_SW_REQ2_CM_IDX] =
|
|
(sw_req2 >> EMI_SW_AP_SHIFT) & EMI_SW_AP_MASK;
|
|
|
|
if (((total_bw_status >> 1) & 0x1) != 0)
|
|
met_vcorefs_src[DDR_EMI_TOTAL_IDX] = 2;
|
|
else if ((total_bw_status & 0x1) != 0)
|
|
met_vcorefs_src[DDR_EMI_TOTAL_IDX] = 1;
|
|
else
|
|
met_vcorefs_src[DDR_EMI_TOTAL_IDX] = 0;
|
|
|
|
if (qos_total_bw > qos1_thres)
|
|
met_vcorefs_src[DDR_QOS_BW_IDX] = 2;
|
|
else if (qos_total_bw > qos0_thres)
|
|
met_vcorefs_src[DDR_QOS_BW_IDX] = 1;
|
|
else
|
|
met_vcorefs_src[DDR_QOS_BW_IDX] = 0;
|
|
|
|
met_vcorefs_src[VCORE_OPP_IDX] = get_cur_vcore_opp();
|
|
|
|
met_vcorefs_src[VCORE_SW_REQ1_PMQOS_IDX] =
|
|
(sw_req >> VCORE_SW_AP_SHIFT) & VCORE_SW_AP_MASK;
|
|
|
|
met_vcorefs_src[VCORE_SW_REQ2_CM_IDX] =
|
|
(sw_req2 >> VCORE_SW_AP_SHIFT) & VCORE_SW_AP_MASK;
|
|
|
|
met_vcorefs_src[VCORE_SCP_IDX] =
|
|
(dvfsrc_read(DVFSRC_VCORE_REQUEST) >> VCORE_SCP_GEAR_SHIFT) &
|
|
VCORE_SCP_GEAR_MASK;
|
|
|
|
met_vcorefs_src[SRC_TOTAL_EMI_BW_IDX] = total_bw_last;
|
|
met_vcorefs_src[SRC_PMQOS_TATOL_IDX] = qos_total_bw * 100;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW0_IDX] =
|
|
dvfsrc_read(DVFSRC_SW_BW_0) * 100;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW1_IDX] =
|
|
dvfsrc_read(DVFSRC_SW_BW_1) * 100;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW2_IDX] =
|
|
dvfsrc_read(DVFSRC_SW_BW_2) * 100;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW3_IDX] =
|
|
dvfsrc_read(DVFSRC_SW_BW_3) * 100;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW4_IDX] =
|
|
dvfsrc_read(DVFSRC_SW_BW_4) * 100;
|
|
|
|
met_vcorefs_src[SRC_MD_REQ_OPP] =
|
|
dvfsrc_read(DVFSRC_RSRV_0);
|
|
|
|
met_vcorefs_src[BWMON_TOTAL_BW_IDX] =
|
|
(qos_sram_read(QOS_DEBUG_0) & 0x7FFFFFFF) ^ 12345600;
|
|
met_vcorefs_src[BWMON_CPU_BW_IDX] =
|
|
(qos_sram_read(QOS_DEBUG_1) & 0x7FFFFFFF) ^ 12345600;
|
|
met_vcorefs_src[BWMON_GPU_BW_IDX] =
|
|
(qos_sram_read(QOS_DEBUG_2) & 0x7FFFFFFF) ^ 12345600;
|
|
met_vcorefs_src[BWMON_MM_BW_IDX] =
|
|
(qos_sram_read(QOS_DEBUG_3) & 0x7FFFFFFF) ^ 12345600;
|
|
return met_vcorefs_src;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_src_req);
|
|
/* gps workarund function */
|
|
static int is_freq_hopping;
|
|
|
|
void dvfsrc_enable_dvfs_freq_hopping(int gps_on)
|
|
{
|
|
static struct mtk_pm_qos_request gps_vcore_req;
|
|
static struct mtk_pm_qos_request gps_ddr_req;
|
|
|
|
if (!is_dvfsrc_enabled())
|
|
return;
|
|
|
|
if (spm_get_spmfw_idx() == SPMFW_LP3_1CH_1866)
|
|
return;
|
|
|
|
if (spm_get_spmfw_idx() == SPMFW_LP4X_2CH_3600)
|
|
return;
|
|
|
|
if (!mtk_pm_qos_request_active(&gps_vcore_req))
|
|
mtk_pm_qos_add_request(&gps_vcore_req,
|
|
MTK_PM_QOS_VCORE_OPP, MTK_PM_QOS_VCORE_OPP_DEFAULT_VALUE);
|
|
|
|
if (!mtk_pm_qos_request_active(&gps_ddr_req))
|
|
mtk_pm_qos_add_request(&gps_ddr_req,
|
|
MTK_PM_QOS_DDR_OPP, MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE);
|
|
|
|
mtk_pm_qos_update_request(&gps_vcore_req, VCORE_OPP_0);
|
|
mtk_pm_qos_update_request(&gps_ddr_req, DDR_OPP_0);
|
|
#if defined(CONFIG_MTK_PMIC_COMMON)
|
|
pr_info("[before]gps_on: %d, vcore: %d ddr: %d dvfsrc_level: 0x%x\n",
|
|
gps_on,
|
|
vcore_pmic_to_uv(pmic_get_register_value(PMIC_VCORE_ADDR)),
|
|
get_dram_data_rate(),
|
|
dvfsrc_read(DVFSRC_LEVEL));
|
|
#endif
|
|
spm_freq_hopping_cmd(!!gps_on);
|
|
|
|
mtk_pm_qos_update_request(&gps_ddr_req, DDR_OPP_UNREQ);
|
|
mtk_pm_qos_update_request(&gps_vcore_req, VCORE_OPP_UNREQ);
|
|
|
|
is_freq_hopping = !!gps_on;
|
|
#if defined(CONFIG_MTK_PMIC_COMMON)
|
|
pr_info("[after]gps_on: %d, vcore: %d ddr: %d dvfsrc_level: 0x%x\n",
|
|
gps_on,
|
|
vcore_pmic_to_uv(pmic_get_register_value(PMIC_VCORE_ADDR)),
|
|
get_dram_data_rate(),
|
|
dvfsrc_read(DVFSRC_LEVEL));
|
|
#endif
|
|
}
|
|
EXPORT_SYMBOL(dvfsrc_enable_dvfs_freq_hopping);
|
|
|
|
int dvfsrc_get_dvfs_freq_hopping_status(void)
|
|
{
|
|
return is_freq_hopping;
|
|
}
|
|
|