72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __HELIO_DVFSRC_MT6885_H
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#define __HELIO_DVFSRC_MT6885_H
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#include <mach/upmu_hw.h>
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#define PMIC_VCORE_ADDR PMIC_RG_BUCK_VGPU11_VOSEL
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#define VCORE_BASE_UV 400000
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#define VCORE_STEP_UV 6250
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#define PMIC_VSRAM_OTHERS_ADDR PMIC_RG_LDO_VSRAM_OTHERS_VOSEL
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#define VSRAM_BASE_UV 500000
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#define VSRAM_STEP_UV 6250
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/* PMIC */
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#define __vcore_pmic_to_uv(pmic) \
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(((pmic) * VCORE_STEP_UV) + VCORE_BASE_UV)
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#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \
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((((uv) - VCORE_BASE_UV) + (VCORE_STEP_UV - 1)) / VCORE_STEP_UV)
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/* VSRAM_OTHERS */
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#define vsram_pmic_to_uv(pmic) \
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(((pmic) * VSRAM_STEP_UV) + VSRAM_BASE_UV)
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#define vsram_uv_to_pmic(uv) /* pmic >= uv */ \
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((((uv) - VSRAM_BASE_UV) + (VSRAM_STEP_UV - 1)) / VSRAM_STEP_UV)
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enum met_src_index {
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SRC_MD2SPM_IDX = 0,
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DDR_OPP_IDX,
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DDR_SW_REQ1_SPM_IDX,
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DDR_SW_REQ2_CM_IDX,
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DDR_SW_REQ3_PMQOS_IDX,
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DDR_SW_REQ4_MD_IDX,
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DDR_SW_REQ8_MCUSYS_IDX,
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DDR_QOS_BW_IDX,
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DDR_EMI_TOTAL_IDX,
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DDR_HRT_BW_IDX,
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DDR_HIFI_IDX,
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DDR_HIFI_LATENCY_IDX,
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DDR_MD_LATENCY_IDX,
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DDR_MD_DDR_IDX,
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DDR_MD_SRCLK_IDX,
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VCORE_OPP_IDX,
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VCORE_SW_REQ3_PMQOS_IDX,
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VCORE_SCP_IDX,
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VCORE_HIFI_IDX,
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SRC_SCP_REQ_IDX,
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SRC_PMQOS_TATOL_IDX,
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SRC_PMQOS_BW0_IDX,
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SRC_PMQOS_BW1_IDX,
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SRC_PMQOS_BW2_IDX,
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SRC_PMQOS_BW3_IDX,
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SRC_PMQOS_BW4_IDX,
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SRC_TOTAL_EMI_BW_IDX,
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SRC_HRT_MD_BW_IDX,
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SRC_HRT_DISP_BW_IDX,
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SRC_HRT_ISP_BW_IDX,
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SRC_MD_SCENARIO_IDX,
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SRC_HIFI_SCENARIO_IDX,
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SRC_MD_EMI_LATENCY_IDX,
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SRC_MAX
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};
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#endif /* __HELIO_DVFSRC_MT6885_H */
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