436 lines
18 KiB
C
436 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_DVFSRC_REG_V2_H
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#define __MTK_DVFSRC_REG_V2_H
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#if defined(CONFIG_MACH_MT6779)
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#define DVFSRC_IP_V2_1
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#elif defined(CONFIG_MACH_MT6785)
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#define DVFSRC_IP_V2_2
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#endif
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/**************************************
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* Define and Declare
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**************************************/
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#define DVFSRC_BASIC_CONTROL (0x0)
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#define DVFSRC_SW_REQ1 (0x4)
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#define DVFSRC_SW_REQ2 (0x8)
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#define DVFSRC_SW_REQ3 (0xC)
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#define DVFSRC_SW_REQ4 (0x10)
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#define DVFSRC_SW_REQ5 (0x14)
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#define DVFSRC_SW_REQ6 (0x18)
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#define DVFSRC_SW_REQ7 (0x1C)
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#define DVFSRC_SW_REQ8 (0x20)
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#define DVFSRC_EMI_REQUEST (0x24)
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#define DVFSRC_EMI_REQUEST2 (0x28)
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#define DVFSRC_EMI_REQUEST3 (0x2C)
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#define DVFSRC_EMI_REQUEST4 (0x30)
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#define DVFSRC_EMI_REQUEST5 (0x34)
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#define DVFSRC_EMI_REQUEST6 (0x38)
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#define DVFSRC_EMI_HRT (0x3C)
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#define DVFSRC_EMI_HRT2 (0x40)
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#define DVFSRC_EMI_HRT3 (0x44)
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#define DVFSRC_EMI_QOS0 (0x48)
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#define DVFSRC_EMI_QOS1 (0x4C)
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#define DVFSRC_EMI_QOS2 (0x50)
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#define DVFSRC_EMI_MD2SPM0 (0x54)
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#define DVFSRC_EMI_MD2SPM1 (0x58)
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#define DVFSRC_EMI_MD2SPM2 (0x5C)
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#define DVFSRC_EMI_MD2SPM0_T (0x60)
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#define DVFSRC_EMI_MD2SPM1_T (0x64)
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#define DVFSRC_EMI_MD2SPM2_T (0x68)
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#define DVFSRC_VCORE_REQUEST (0x6C)
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#define DVFSRC_VCORE_REQUEST2 (0x70)
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#define DVFSRC_VCORE_REQUEST3 (0x74)
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#define DVFSRC_VCORE_REQUEST4 (0x78)
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#define DVFSRC_VCORE_HRT (0x7C)
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#define DVFSRC_VCORE_HRT2 (0x80)
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#define DVFSRC_VCORE_HRT3 (0x84)
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#define DVFSRC_VCORE_QOS0 (0x88)
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#define DVFSRC_VCORE_QOS1 (0x8C)
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#define DVFSRC_VCORE_QOS2 (0x90)
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#define DVFSRC_VCORE_MD2SPM0 (0x94)
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#define DVFSRC_VCORE_MD2SPM1 (0x98)
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#define DVFSRC_VCORE_MD2SPM2 (0x9C)
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#define DVFSRC_VCORE_MD2SPM0_T (0xA0)
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#define DVFSRC_VCORE_MD2SPM1_T (0xA4)
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#define DVFSRC_VCORE_MD2SPM2_T (0xA8)
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#define DVFSRC_MD_VSRAM_REMAP (0xBC)
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#define DVFSRC_HALT_SW_CONTROL (0xC0)
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#define DVFSRC_INT (0xC4)
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#define DVFSRC_INT_EN (0xC8)
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#define DVFSRC_INT_CLR (0xCC)
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#define DVFSRC_BW_MON_WINDOW (0xD0)
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#define DVFSRC_BW_MON_THRES_1 (0xD4)
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#define DVFSRC_BW_MON_THRES_2 (0xD8)
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#define DVFSRC_MD_TURBO (0xDC)
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#define DVFSRC_PCIE_VCORE_REQ (0xE0)
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#define DVFSRC_VCORE_USER_REQ (0xE4)
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#define DVFSRC_BW_USER_REQ (0xE8)
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#define DVFSRC_DEBOUNCE_FOUR (0xF0)
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#define DVFSRC_DEBOUNCE_RISE_FALL (0xF4)
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#define DVFSRC_TIMEOUT_NEXTREQ (0xF8)
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#define DVFSRC_LEVEL_LABEL_0_1 (0x100)
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#define DVFSRC_LEVEL_LABEL_2_3 (0x104)
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#define DVFSRC_LEVEL_LABEL_4_5 (0x108)
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#define DVFSRC_LEVEL_LABEL_6_7 (0x10C)
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#define DVFSRC_LEVEL_LABEL_8_9 (0x110)
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#define DVFSRC_LEVEL_LABEL_10_11 (0x114)
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#define DVFSRC_LEVEL_LABEL_12_13 (0x118)
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#define DVFSRC_LEVEL_LABEL_14_15 (0x11C)
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#define DVFSRC_MM_BW_0 (0x200)
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#define DVFSRC_MM_BW_1 (0x204)
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#define DVFSRC_MM_BW_2 (0x208)
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#define DVFSRC_MM_BW_3 (0x20C)
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#define DVFSRC_MM_BW_4 (0x210)
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#define DVFSRC_MM_BW_5 (0x214)
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#define DVFSRC_MM_BW_6 (0x218)
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#define DVFSRC_MM_BW_7 (0x21C)
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#define DVFSRC_MM_BW_8 (0x220)
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#define DVFSRC_MM_BW_9 (0x224)
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#define DVFSRC_MM_BW_10 (0x228)
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#define DVFSRC_MM_BW_11 (0x22C)
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#define DVFSRC_MM_BW_12 (0x230)
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#define DVFSRC_MM_BW_13 (0x234)
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#define DVFSRC_MM_BW_14 (0x238)
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#define DVFSRC_MM_BW_15 (0x23C)
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#define DVFSRC_MD_BW_0 (0x240)
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#define DVFSRC_MD_BW_1 (0x244)
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#define DVFSRC_MD_BW_2 (0x248)
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#define DVFSRC_MD_BW_3 (0x24C)
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#define DVFSRC_MD_BW_4 (0x250)
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#define DVFSRC_MD_BW_5 (0x254)
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#define DVFSRC_MD_BW_6 (0x258)
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#define DVFSRC_MD_BW_7 (0x25C)
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#define DVFSRC_SW_BW_0 (0x260)
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#define DVFSRC_SW_BW_1 (0x264)
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#define DVFSRC_SW_BW_2 (0x268)
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#define DVFSRC_SW_BW_3 (0x26C)
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#define DVFSRC_SW_BW_4 (0x270)
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#define DVFSRC_SW_BW_5 (0x274)
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#define DVFSRC_SW_BW_6 (0x278)
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#define DVFSRC_QOS_EN (0x280)
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#define DVFSRC_MD_BW_URG (0x284)
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#define DVFSRC_ISP_HRT (0x290)
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#define DVFSRC_HRT_BW_BASE (0x294)
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#define DVFSRC_SEC_SW_REQ (0x304)
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#define DVFSRC_EMI_MON_DEBOUNCE_TIME (0x308)
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#define DVFSRC_MD_LATENCY_IMPROVE (0x30C)
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#define DVFSRC_BASIC_CONTROL_3 (0x310)
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#define DVFSRC_DEBOUNCE_TIME (0x314)
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#define DVFSRC_LEVEL_MASK (0x318)
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#define DVFSRC_DEFAULT_OPP (0x31C)
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#define DVFSRC_95MD_SCEN_EMI0 (0x500)
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#define DVFSRC_95MD_SCEN_EMI1 (0x504)
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#define DVFSRC_95MD_SCEN_EMI2 (0x508)
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#define DVFSRC_95MD_SCEN_EMI3 (0x50C)
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#define DVFSRC_95MD_SCEN_EMI0_T (0x510)
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#define DVFSRC_95MD_SCEN_EMI1_T (0x514)
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#define DVFSRC_95MD_SCEN_EMI2_T (0x518)
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#define DVFSRC_95MD_SCEN_EMI3_T (0x51C)
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#define DVFSRC_95MD_SCEN_EMI4 (0x520)
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#define DVFSRC_95MD_SCEN_BW0 (0x524)
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#define DVFSRC_95MD_SCEN_BW1 (0x528)
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#define DVFSRC_95MD_SCEN_BW2 (0x52C)
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#define DVFSRC_95MD_SCEN_BW3 (0x530)
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#define DVFSRC_95MD_SCEN_BW0_T (0x534)
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#define DVFSRC_95MD_SCEN_BW1_T (0x538)
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#define DVFSRC_95MD_SCEN_BW2_T (0x53C)
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#define DVFSRC_95MD_SCEN_BW3_T (0x540)
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#define DVFSRC_95MD_SCEN_BW4 (0x544)
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#define DVFSRC_MD_LEVEL_SW_REG (0x548)
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#define DVFSRC_RSRV_0 (0x600)
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#define DVFSRC_RSRV_1 (0x604)
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#define DVFSRC_RSRV_2 (0x608)
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#define DVFSRC_RSRV_3 (0x60C)
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#define DVFSRC_RSRV_4 (0x610)
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#define DVFSRC_RSRV_5 (0x614)
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#define DVFSRC_SPM_RESEND (0x630)
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#define DVFSRC_DEBUG_STA_0 (0x700)
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#define DVFSRC_DEBUG_STA_1 (0x704)
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#define DVFSRC_DEBUG_STA_2 (0x708)
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#define DVFSRC_DEBUG_STA_3 (0x70C)
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#define DVFSRC_DEBUG_STA_4 (0x710)
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#define DVFSRC_DEBUG_STA_5 (0x714)
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#define DVFSRC_DEBUG_STA_6 (0x718)
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#define DVFSRC_EMI_REQUEST7 (0x800)
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#define DVFSRC_EMI_HRT_1 (0x804)
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#define DVFSRC_EMI_HRT2_1 (0x808)
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#define DVFSRC_EMI_HRT3_1 (0x80C)
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#define DVFSRC_EMI_QOS3 (0x810)
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#define DVFSRC_EMI_QOS4 (0x814)
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#define DVFSRC_DDR_REQUEST (0xA00)
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#define DVFSRC_DDR_REQUEST2 (0xA04)
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#define DVFSRC_DDR_REQUEST3 (0xA08)
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#define DVFSRC_DDR_REQUEST4 (0xA0C)
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#define DVFSRC_DDR_REQUEST5 (0xA10)
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#define DVFSRC_DDR_REQUEST6 (0xA14)
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#define DVFSRC_DDR_REQUEST7 (0xA18)
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#define DVFSRC_DDR_HRT (0xA1C)
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#define DVFSRC_DDR_HRT2 (0xA20)
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#define DVFSRC_DDR_HRT3 (0xA24)
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#define DVFSRC_DDR_HRT_1 (0xA28)
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#define DVFSRC_DDR_HRT2_1 (0xA2C)
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#define DVFSRC_DDR_HRT3_1 (0xA30)
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#define DVFSRC_DDR_QOS0 (0xA34)
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#define DVFSRC_DDR_QOS1 (0xA38)
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#define DVFSRC_DDR_QOS2 (0xA3C)
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#define DVFSRC_DDR_QOS3 (0xA40)
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#define DVFSRC_DDR_QOS4 (0xA44)
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#define DVFSRC_DDR_MD2SPM0 (0xA48)
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#define DVFSRC_DDR_MD2SPM1 (0xA4C)
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#define DVFSRC_DDR_MD2SPM2 (0xA50)
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#define DVFSRC_DDR_MD2SPM0_T (0xA54)
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#define DVFSRC_DDR_MD2SPM1_T (0xA58)
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#define DVFSRC_DDR_MD2SPM2_T (0xA5C)
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#if defined(DVFSRC_IP_V2_1)
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#define DVFSRC_HRT_REQ_UNIT (0xA84)
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#define DVSFRC_HRT_REQ_MD_URG (0xA88)
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#define DVFSRC_HRT_REQ_MD_BW_0 (0xA8C)
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#define DVFSRC_HRT_REQ_MD_BW_1 (0xA90)
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#define DVFSRC_HRT_REQ_MD_BW_2 (0xA94)
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#define DVFSRC_HRT_REQ_MD_BW_3 (0xA98)
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#define DVFSRC_HRT_REQ_MD_BW_4 (0xA9C)
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#define DVFSRC_HRT_REQ_MD_BW_5 (0xAA0)
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#define DVFSRC_HRT_REQ_MD_BW_6 (0xAA4)
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#define DVFSRC_HRT_REQ_MD_BW_7 (0xAA8)
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#define DVFSRC_HRT1_REQ_MD_BW_0 (0xAAC)
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#define DVFSRC_HRT1_REQ_MD_BW_1 (0xAB0)
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#define DVFSRC_HRT1_REQ_MD_BW_2 (0xAB4)
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#define DVFSRC_HRT1_REQ_MD_BW_3 (0xAB8)
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#define DVFSRC_HRT1_REQ_MD_BW_4 (0xABC)
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#define DVFSRC_HRT1_REQ_MD_BW_5 (0xAC0)
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#define DVFSRC_HRT1_REQ_MD_BW_6 (0xAC4)
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#define DVFSRC_HRT1_REQ_MD_BW_7 (0xAC8)
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#define DVFSRC_HRT_REQ_MD_BW_8 (0xACC)
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#define DVFSRC_HRT_REQ_MD_BW_9 (0xAD0)
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#define DVFSRC_HRT_REQ_MD_BW_10 (0xAD4)
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#define DVFSRC_HRT1_REQ_MD_BW_8 (0xAD8)
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#define DVFSRC_HRT1_REQ_MD_BW_9 (0xADC)
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#define DVFSRC_HRT1_REQ_MD_BW_10 (0xAE0)
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#define DVFSRC_HRT_REQ_BW_SW_REG (0xAE4)
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#define DVFSRC_HRT_REQUEST (0xAE8)
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#define DVFSRC_HRT_HIGH_2 (0xAEC)
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#define DVFSRC_HRT_HIGH_1 (0xAF0)
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#define DVFSRC_HRT_HIGH (0xAF4)
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#define DVFSRC_HRT_LOW_2 (0xAF8)
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#define DVFSRC_HRT_LOW_1 (0xAFC)
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#define DVFSRC_HRT_LOW (0xB00)
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#define DVFSRC_DDR_ADD_REQUEST (0xB04)
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#define DVFSRC_LAST (0xB08)
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#define DVFSRC_LAST_L (0xB0C)
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#define DVFSRC_MD_SCENARIO (0xB10)
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#define DVFSRC_RECORD_0_0 (0xB14)
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#define DVFSRC_RECORD_0_1 (0xB18)
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#define DVFSRC_RECORD_0_2 (0xB1C)
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#define DVFSRC_RECORD_0_3 (0xB20)
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#define DVFSRC_RECORD_0_4 (0xB24)
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#define DVFSRC_RECORD_0_5 (0xB28)
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#define DVFSRC_RECORD_0_6 (0xB2C)
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#define DVFSRC_RECORD_0_L_0 (0xBF4)
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#define DVFSRC_RECORD_0_L_1 (0xBF8)
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#define DVFSRC_RECORD_0_L_2 (0xBFC)
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#define DVFSRC_RECORD_0_L_3 (0xC00)
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#define DVFSRC_RECORD_0_L_4 (0xC04)
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#define DVFSRC_RECORD_0_L_5 (0xC08)
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#define DVFSRC_RECORD_0_L_6 (0xC0C)
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#else
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#define DVFSRC_HRT_REQ_UNIT (0xA60)
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#define DVSFRC_HRT_REQ_MD_URG (0xA64)
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#define DVFSRC_HRT_REQ_MD_BW_0 (0xA68)
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#define DVFSRC_HRT_REQ_MD_BW_1 (0xA6C)
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#define DVFSRC_HRT_REQ_MD_BW_2 (0xA70)
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#define DVFSRC_HRT_REQ_MD_BW_3 (0xA74)
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#define DVFSRC_HRT_REQ_MD_BW_4 (0xA78)
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#define DVFSRC_HRT_REQ_MD_BW_5 (0xA7C)
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#define DVFSRC_HRT_REQ_MD_BW_6 (0xA80)
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#define DVFSRC_HRT_REQ_MD_BW_7 (0xA84)
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#define DVFSRC_HRT1_REQ_MD_BW_0 (0xA88)
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#define DVFSRC_HRT1_REQ_MD_BW_1 (0xA8C)
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#define DVFSRC_HRT1_REQ_MD_BW_2 (0xA90)
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#define DVFSRC_HRT1_REQ_MD_BW_3 (0xA94)
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#define DVFSRC_HRT1_REQ_MD_BW_4 (0xA98)
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#define DVFSRC_HRT1_REQ_MD_BW_5 (0xA9C)
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#define DVFSRC_HRT1_REQ_MD_BW_6 (0xAA0)
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#define DVFSRC_HRT1_REQ_MD_BW_7 (0xAA4)
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#define DVFSRC_HRT_REQ_MD_BW_8 (0xAA8)
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#define DVFSRC_HRT_REQ_MD_BW_9 (0xAAC)
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#define DVFSRC_HRT_REQ_MD_BW_10 (0xAB0)
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#define DVFSRC_HRT1_REQ_MD_BW_8 (0xAB4)
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#define DVFSRC_HRT1_REQ_MD_BW_9 (0xAB8)
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#define DVFSRC_HRT1_REQ_MD_BW_10 (0xABC)
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#define DVFSRC_HRT_REQ_BW_SW_REG (0xAC0)
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#define DVFSRC_HRT_REQUEST (0xAC4)
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#define DVFSRC_HRT_HIGH_2 (0xAC8)
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#define DVFSRC_HRT_HIGH_1 (0xACC)
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#define DVFSRC_HRT_HIGH (0xAD0)
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#define DVFSRC_HRT_LOW_2 (0xAD4)
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#define DVFSRC_HRT_LOW_1 (0xAD8)
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#define DVFSRC_HRT_LOW (0xADC)
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#define DVFSRC_DDR_ADD_REQUEST (0xAE0)
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#define DVFSRC_LAST (0xAE4)
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#define DVFSRC_LAST_L (0xAE8)
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#define DVFSRC_MD_SCENARIO (0xAEC)
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#define DVFSRC_RECORD_0_0 (0xAF0)
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#define DVFSRC_RECORD_0_1 (0xAF4)
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#define DVFSRC_RECORD_0_2 (0xAF8)
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#define DVFSRC_RECORD_0_3 (0xAFC)
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#define DVFSRC_RECORD_0_4 (0xB00)
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#define DVFSRC_RECORD_0_5 (0xB04)
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#define DVFSRC_RECORD_0_6 (0xB08)
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#define DVFSRC_RECORD_0_7 (0xB0C)
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#define DVFSRC_RECORD_0_L_0 (0xBF0)
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#define DVFSRC_RECORD_0_L_1 (0xBF4)
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#define DVFSRC_RECORD_0_L_2 (0xBF8)
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#define DVFSRC_RECORD_0_L_3 (0xBFC)
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#define DVFSRC_RECORD_0_L_4 (0xC00)
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#define DVFSRC_RECORD_0_L_5 (0xC04)
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#define DVFSRC_RECORD_0_L_6 (0xC08)
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#define DVFSRC_RECORD_0_L_7 (0xC0C)
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#endif
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#define DVFSRC_EMI_REQUEST8 (0xCF0)
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#define DVFSRC_DDR_REQUEST8 (0xCF4)
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#define DVFSRC_EMI_HRT_2 (0xCF8)
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#define DVFSRC_EMI_HRT2_2 (0xCFC)
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#define DVFSRC_EMI_HRT3_2 (0xD00)
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#define DVFSRC_EMI_QOS5 (0xD04)
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#define DVFSRC_EMI_QOS6 (0xD08)
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#define DVFSRC_DDR_HRT_2 (0xD0C)
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#define DVFSRC_DDR_HRT2_2 (0xD10)
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#define DVFSRC_DDR_HRT3_2 (0xD14)
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#define DVFSRC_DDR_QOS5 (0xD18)
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#define DVFSRC_DDR_QOS6 (0xD1C)
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#define DVFSRC_VCORE_REQUEST5 (0xD20)
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#define DVFSRC_VCORE_HRT_1 (0xD24)
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#define DVFSRC_VCORE_HRT2_1 (0xD28)
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#define DVFSRC_VCORE_HRT3_1 (0xD2C)
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#define DVFSRC_VCORE_QOS3 (0xD30)
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#define DVFSRC_VCORE_QOS4 (0xD34)
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#define DVFSRC_HRT_HIGH_3 (0xD38)
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#define DVFSRC_HRT_LOW_3 (0xD3C)
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#define DVFSRC_BASIC_CONTROL_2 (0xD40)
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#define DVFSRC_CURRENT_LEVEL (0xD44)
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#define DVFSRC_TARGET_LEVEL (0xD48)
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#define DVFSRC_LEVEL_LABEL_16_17 (0xD4C)
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#define DVFSRC_LEVEL_LABEL_18_19 (0xD50)
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#define DVFSRC_LEVEL_LABEL_20_21 (0xD54)
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#define DVFSRC_LEVEL_LABEL_22_23 (0xD58)
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#define DVFSRC_LEVEL_LABEL_24_25 (0xD5C)
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#define DVFSRC_LEVEL_LABEL_26_27 (0xD60)
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#define DVFSRC_LEVEL_LABEL_28_29 (0xD64)
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#define DVFSRC_LEVEL_LABEL_30_31 (0xD68)
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#define DVFSRC_CURRENT_FORCE (0xD6C)
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#define DVFSRC_TARGET_FORCE (0xD70)
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#define DVFSRC_EMI_ADD_REQUEST (0xD74)
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/* DVFSRC_BASIC_CONTROL 0x0 */
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#define DVFSRC_EN_SHIFT 0
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#define DVFSRC_EN_MASK 0x1
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#define DVFSRC_OUT_EN_SHIFT 8
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#define DVFSRC_OUT_EN_MASK 0x1
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#define FORCE_EN_CUR_SHIFT 14
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#define FORCE_EN_CUR_MASK 0x1
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#define FORCE_EN_TAR_SHIFT 15
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#define FORCE_EN_TAR_MASK 0x1
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/* DVFSRC_SW_REQX */
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#define DDR_SW_AP_SHIFT 12
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#define DDR_SW_AP_MASK 0x7
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#define VCORE_SW_AP_SHIFT 4
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#define VCORE_SW_AP_MASK 0x7
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#define EMI_SW_AP_SHIFT 0
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#define EMI_SW_AP_MASK 0x7
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/* DVFSRC_VCORE_REQUEST 0x70 */
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#define VCORE_SCP_GEAR_SHIFT 12
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#define VCORE_SCP_GEAR_MASK 0x7
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/* DVFSRC_LEVEL 0xFC */
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#define CURRENT_LEVEL_SHIFT 0
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#define CURRENT_LEVEL_MASK 0xFFFFFFFF
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/* DVFSRC_FORCE 0x300 */
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#define TARGET_FORCE_SHIFT 0
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#define TARGET_FORCE_MASK 0xFFFFFFFF
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#define CURRENT_FORCE_SHIFT 0
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#define CURRENT_FORCE_MASK 0xFFFFFFFF
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/* DVFSRC_DEBUG_STA_0 */
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#define MD_EMI_URG_DEBUG_SHIFT 16
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#define MD_EMI_URG_DEBUG_MASK 0x1
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#define MD_SRC_CLK_DEBUG_SHIFT 17
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#define MD_SRC_CLK_DEBUG_MASK 0x1
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#define MD_EMI_VAL_DEBUG_SHIFT 0
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#define MD_EMI_VAL_DEBUG_MASK 0xFFFF
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/* DVFSRC_DEBUG_STA_4 */
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#define MD_EMI_MD_IMP_SHIFT 19
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#define MD_EMI_MD_IMP_MASK 0x7
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/* DVSFRC_HRT_REQ_MD_URG */
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#define MD_HRT_BW_URG_SHIFT 0
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#define MD_HRT_BW_URG_MASK 0xFF
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#define MD_HRT_BW_URG1_SHIFT 8
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#define MD_HRT_BW_URG1_MASK 0xFF
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/* DVFSRC_HRTX_REQ_MD_BW_x */
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#define MD_HRT_BW_MASK 0x3FF
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#define DEBUG_MDTURBO_SHIFT 18
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#define DEBUG_MDTURBO_MASK 0x1
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#define DEBUG_MD_RIS_DDR_SHIFT 29
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#define DEBUG_MD_RIS_DDR_MASK 0x7
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#define DEBUG_HIFI_RIS_DDR_SHIFT 22
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#define DEBUG_HIFI_RIS_DDR_MASK 0x7
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#define DEBUG_STA2_EMI_TOTAL_SHIFT 0
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#define DEBUG_STA2_EMI_TOTAL_MASK 0xFFF
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#define DEBUG_STA2_SCP_SHIFT 14
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#define DEBUG_STA2_SCP_MASK 0x1
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#define DEBUG_STA2_PCIE_SHIFT 27
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#define DEBUG_STA2_PCIE_MASK 0x1
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#define DEBUG_STA2_MD_EMI_LATENCY_SHIFT 12
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#define DEBUG_STA2_MD_EMI_LATENCY_MASK 0x3
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#define DEBUG_STA2_HIFI_SCENARIO_SHIFT 16
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#define DEBUG_STA2_HIFI_SCENARIO_MASK 0xFF
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#define DEBUG_STA4_HRT_BW_REQ_SHIFT 16
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#define DEBUG_STA4_HRT_BW_REQ_MASK 0x7
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#define DEBUG_STA3_MD_HRT_BW_SHIFT 0
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#define DEBUG_STA3_MD_HRT_BW_MASK 0x3FF
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#if defined(DVFSRC_IP_V2_1)
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#define RECORD_SHIFT 0x1C
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#else
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#define RECORD_SHIFT 0x20
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#endif
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#if defined(DVFSRC_IP_V2_1)
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#define MD_TURBO_SWITCH_SHIFT 5
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#define MD_TURBO_SWITCH_MASK 0x1
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#define RECORD_HIFI_DDR_LATENCY_REQ 15
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#define RECORD_HIFI_DDR_LATENCY_MASK 0x7
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#define RECORD_HRT_BW_REQ_SHIFT 2
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#define RECORD_HRT_BW_REQ_MASK 0x7
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#define RECORD_MD_DDR_LATENCY_REQ 9
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#define RECORD_MD_DDR_LATENCY_MASK 0x7
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#elif defined(DVFSRC_IP_V2_2)
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#define RECORD_HRT_BW_REQ_SHIFT 21
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#define RECORD_HRT_BW_REQ_MASK 0x7
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#endif
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#endif /* __MTK_DVFSRC_REG_V2_H */
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