75 lines
2.7 KiB
C
75 lines
2.7 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_JOB_H__
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#define __AMDGPU_JOB_H__
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/* bit set means command submit involves a preamble IB */
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#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0)
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/* bit set means preamble IB is first presented in belonging context */
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#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1)
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/* bit set means context switch occured */
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#define AMDGPU_HAVE_CTX_SWITCH (1 << 2)
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#define to_amdgpu_job(sched_job) \
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container_of((sched_job), struct amdgpu_job, base)
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struct amdgpu_fence;
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struct amdgpu_job {
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struct drm_sched_job base;
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struct amdgpu_vm *vm;
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struct amdgpu_sync sync;
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struct amdgpu_sync sched_sync;
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struct amdgpu_ib *ibs;
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struct dma_fence *fence; /* the hw fence */
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uint32_t preamble_status;
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uint32_t num_ibs;
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void *owner;
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bool vm_needs_flush;
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uint64_t vm_pd_addr;
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unsigned vmid;
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unsigned pasid;
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uint32_t gds_base, gds_size;
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uint32_t gws_base, gws_size;
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uint32_t oa_base, oa_size;
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uint32_t vram_lost_counter;
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/* user fence handling */
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uint64_t uf_addr;
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uint64_t uf_sequence;
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};
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int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
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struct amdgpu_job **job, struct amdgpu_vm *vm);
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int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
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struct amdgpu_job **job);
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void amdgpu_job_free_resources(struct amdgpu_job *job);
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void amdgpu_job_free(struct amdgpu_job *job);
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int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
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void *owner, struct dma_fence **f);
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int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
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struct dma_fence **fence);
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#endif
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