755 lines
20 KiB
C
755 lines
20 KiB
C
/*
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* Copyright 2012-14 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DC_INTERFACE_H_
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#define DC_INTERFACE_H_
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#include "dc_types.h"
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#include "grph_object_defs.h"
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#include "logger_types.h"
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#include "gpio_types.h"
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#include "link_service_types.h"
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#include "grph_object_ctrl_defs.h"
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#include <inc/hw/opp.h>
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#include "inc/hw_sequencer.h"
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#include "inc/compressor.h"
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#include "dml/display_mode_lib.h"
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#define DC_VER "3.1.59"
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#define MAX_SURFACES 3
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#define MAX_STREAMS 6
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#define MAX_SINKS_PER_LINK 4
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/*******************************************************************************
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* Display Core Interfaces
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******************************************************************************/
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struct dmcu_version {
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unsigned int date;
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unsigned int month;
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unsigned int year;
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unsigned int interface_version;
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};
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struct dc_versions {
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const char *dc_ver;
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struct dmcu_version dmcu_version;
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};
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struct dc_caps {
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uint32_t max_streams;
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uint32_t max_links;
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uint32_t max_audios;
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uint32_t max_slave_planes;
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uint32_t max_planes;
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uint32_t max_downscale_ratio;
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uint32_t i2c_speed_in_khz;
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uint32_t dmdata_alloc_size;
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unsigned int max_cursor_size;
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unsigned int max_video_width;
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int linear_pitch_alignment;
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bool dcc_const_color;
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bool dynamic_audio;
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bool is_apu;
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bool dual_link_dvi;
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bool post_blend_color_processing;
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bool force_dp_tps4_for_cp2520;
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bool disable_dp_clk_share;
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bool psp_setup_panel_mode;
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};
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struct dc_dcc_surface_param {
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struct dc_size surface_size;
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enum surface_pixel_format format;
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enum swizzle_mode_values swizzle_mode;
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enum dc_scan_direction scan;
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};
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struct dc_dcc_setting {
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unsigned int max_compressed_blk_size;
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unsigned int max_uncompressed_blk_size;
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bool independent_64b_blks;
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};
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struct dc_surface_dcc_cap {
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union {
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struct {
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struct dc_dcc_setting rgb;
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} grph;
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struct {
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struct dc_dcc_setting luma;
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struct dc_dcc_setting chroma;
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} video;
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};
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bool capable;
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bool const_color_support;
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};
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struct dc_static_screen_events {
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bool force_trigger;
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bool cursor_update;
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bool surface_update;
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bool overlay_update;
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};
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/* Surface update type is used by dc_update_surfaces_and_stream
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* The update type is determined at the very beginning of the function based
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* on parameters passed in and decides how much programming (or updating) is
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* going to be done during the call.
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*
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* UPDATE_TYPE_FAST is used for really fast updates that do not require much
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* logical calculations or hardware register programming. This update MUST be
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* ISR safe on windows. Currently fast update will only be used to flip surface
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* address.
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*
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* UPDATE_TYPE_MED is used for slower updates which require significant hw
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* re-programming however do not affect bandwidth consumption or clock
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* requirements. At present, this is the level at which front end updates
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* that do not require us to run bw_calcs happen. These are in/out transfer func
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* updates, viewport offset changes, recout size changes and pixel depth changes.
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* This update can be done at ISR, but we want to minimize how often this happens.
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*
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* UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
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* bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
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* end related. Any time viewport dimensions, recout dimensions, scaling ratios or
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* gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
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* a full update. This cannot be done at ISR level and should be a rare event.
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* Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
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* underscan we don't expect to see this call at all.
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*/
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enum surface_update_type {
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UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
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UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
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UPDATE_TYPE_FULL, /* may need to shuffle resources */
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};
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/* Forward declaration*/
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struct dc;
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struct dc_plane_state;
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struct dc_state;
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struct dc_cap_funcs {
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bool (*get_dcc_compression_cap)(const struct dc *dc,
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const struct dc_dcc_surface_param *input,
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struct dc_surface_dcc_cap *output);
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};
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struct link_training_settings;
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/* Structure to hold configuration flags set by dm at dc creation. */
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struct dc_config {
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bool gpu_vm_support;
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bool disable_disp_pll_sharing;
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};
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enum visual_confirm {
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VISUAL_CONFIRM_DISABLE = 0,
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VISUAL_CONFIRM_SURFACE = 1,
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VISUAL_CONFIRM_HDR = 2,
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};
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enum dcc_option {
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DCC_ENABLE = 0,
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DCC_DISABLE = 1,
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DCC_HALF_REQ_DISALBE = 2,
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};
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enum pipe_split_policy {
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MPC_SPLIT_DYNAMIC = 0,
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MPC_SPLIT_AVOID = 1,
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MPC_SPLIT_AVOID_MULT_DISP = 2,
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};
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enum wm_report_mode {
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WM_REPORT_DEFAULT = 0,
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WM_REPORT_OVERRIDE = 1,
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};
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/*
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* For any clocks that may differ per pipe
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* only the max is stored in this structure
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*/
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struct dc_clocks {
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int dispclk_khz;
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int max_supported_dppclk_khz;
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int dppclk_khz;
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int dcfclk_khz;
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int socclk_khz;
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int dcfclk_deep_sleep_khz;
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int fclk_khz;
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int phyclk_khz;
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};
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struct dc_debug_options {
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enum visual_confirm visual_confirm;
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bool sanity_checks;
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bool max_disp_clk;
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bool surface_trace;
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bool timing_trace;
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bool clock_trace;
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bool validation_trace;
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bool bandwidth_calcs_trace;
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int max_downscale_src_width;
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/* stutter efficiency related */
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bool disable_stutter;
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bool use_max_lb;
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enum dcc_option disable_dcc;
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enum pipe_split_policy pipe_split_policy;
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bool force_single_disp_pipe_split;
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bool voltage_align_fclk;
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bool disable_dfs_bypass;
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bool disable_dpp_power_gate;
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bool disable_hubp_power_gate;
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bool disable_pplib_wm_range;
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enum wm_report_mode pplib_wm_report_mode;
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unsigned int min_disp_clk_khz;
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int sr_exit_time_dpm0_ns;
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int sr_enter_plus_exit_time_dpm0_ns;
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int sr_exit_time_ns;
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int sr_enter_plus_exit_time_ns;
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int urgent_latency_ns;
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int percent_of_ideal_drambw;
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int dram_clock_change_latency_ns;
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bool optimized_watermark;
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int always_scale;
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bool disable_pplib_clock_request;
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bool disable_clock_gate;
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bool disable_dmcu;
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bool disable_psr;
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bool force_abm_enable;
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bool disable_hbup_pg;
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bool disable_dpp_pg;
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bool disable_stereo_support;
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bool vsr_support;
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bool performance_trace;
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bool az_endpoint_mute_only;
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bool always_use_regamma;
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bool p010_mpo_support;
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bool recovery_enabled;
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bool avoid_vbios_exec_table;
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bool scl_reset_length10;
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bool hdmi20_disable;
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bool skip_detection_link_training;
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};
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struct dc_debug_data {
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uint32_t ltFailCount;
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uint32_t i2cErrorCount;
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uint32_t auxErrorCount;
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};
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struct dc_state;
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struct resource_pool;
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struct dce_hwseq;
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struct dc {
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struct dc_versions versions;
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struct dc_caps caps;
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struct dc_cap_funcs cap_funcs;
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struct dc_config config;
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struct dc_debug_options debug;
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struct dc_context *ctx;
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uint8_t link_count;
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struct dc_link *links[MAX_PIPES * 2];
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struct dc_state *current_state;
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struct resource_pool *res_pool;
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/* Display Engine Clock levels */
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struct dm_pp_clock_levels sclk_lvls;
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/* Inputs into BW and WM calculations. */
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struct bw_calcs_dceip *bw_dceip;
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struct bw_calcs_vbios *bw_vbios;
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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struct dcn_soc_bounding_box *dcn_soc;
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struct dcn_ip_params *dcn_ip;
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struct display_mode_lib dml;
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#endif
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/* HW functions */
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struct hw_sequencer_funcs hwss;
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struct dce_hwseq *hwseq;
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/* temp store of dm_pp_display_configuration
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* to compare to see if display config changed
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*/
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struct dm_pp_display_configuration prev_display_config;
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bool optimized_required;
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bool apply_edp_fast_boot_optimization;
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/* FBC compressor */
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struct compressor *fbc_compressor;
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struct dc_debug_data debug_data;
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};
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enum frame_buffer_mode {
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FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
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FRAME_BUFFER_MODE_ZFB_ONLY,
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FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
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} ;
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struct dchub_init_data {
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int64_t zfb_phys_addr_base;
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int64_t zfb_mc_base_addr;
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uint64_t zfb_size_in_byte;
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enum frame_buffer_mode fb_mode;
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bool dchub_initialzied;
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bool dchub_info_valid;
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};
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struct dc_init_data {
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struct hw_asic_id asic_id;
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void *driver; /* ctx */
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struct cgs_device *cgs_device;
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int num_virtual_links;
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/*
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* If 'vbios_override' not NULL, it will be called instead
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* of the real VBIOS. Intended use is Diagnostics on FPGA.
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*/
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struct dc_bios *vbios_override;
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enum dce_environment dce_environment;
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struct dc_config flags;
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uint32_t log_mask;
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};
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struct dc *dc_create(const struct dc_init_data *init_params);
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void dc_destroy(struct dc **dc);
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/*******************************************************************************
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* Surface Interfaces
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******************************************************************************/
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enum {
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TRANSFER_FUNC_POINTS = 1025
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};
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struct dc_hdr_static_metadata {
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/* display chromaticities and white point in units of 0.00001 */
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unsigned int chromaticity_green_x;
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unsigned int chromaticity_green_y;
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unsigned int chromaticity_blue_x;
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unsigned int chromaticity_blue_y;
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unsigned int chromaticity_red_x;
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unsigned int chromaticity_red_y;
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unsigned int chromaticity_white_point_x;
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unsigned int chromaticity_white_point_y;
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uint32_t min_luminance;
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uint32_t max_luminance;
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uint32_t maximum_content_light_level;
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uint32_t maximum_frame_average_light_level;
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};
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enum dc_transfer_func_type {
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TF_TYPE_PREDEFINED,
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TF_TYPE_DISTRIBUTED_POINTS,
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TF_TYPE_BYPASS,
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TF_TYPE_HWPWL
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};
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struct dc_transfer_func_distributed_points {
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struct fixed31_32 red[TRANSFER_FUNC_POINTS];
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struct fixed31_32 green[TRANSFER_FUNC_POINTS];
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struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
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uint16_t end_exponent;
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uint16_t x_point_at_y1_red;
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uint16_t x_point_at_y1_green;
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uint16_t x_point_at_y1_blue;
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};
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enum dc_transfer_func_predefined {
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TRANSFER_FUNCTION_SRGB,
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TRANSFER_FUNCTION_BT709,
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TRANSFER_FUNCTION_PQ,
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TRANSFER_FUNCTION_LINEAR,
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TRANSFER_FUNCTION_UNITY,
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TRANSFER_FUNCTION_HLG,
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TRANSFER_FUNCTION_HLG12,
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TRANSFER_FUNCTION_GAMMA22
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};
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struct dc_transfer_func {
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struct kref refcount;
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enum dc_transfer_func_type type;
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enum dc_transfer_func_predefined tf;
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/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
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uint32_t sdr_ref_white_level;
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struct dc_context *ctx;
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union {
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struct pwl_params pwl;
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struct dc_transfer_func_distributed_points tf_pts;
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};
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};
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/*
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* This structure is filled in by dc_surface_get_status and contains
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* the last requested address and the currently active address so the called
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* can determine if there are any outstanding flips
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*/
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struct dc_plane_status {
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struct dc_plane_address requested_address;
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struct dc_plane_address current_address;
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bool is_flip_pending;
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bool is_right_eye;
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};
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union surface_update_flags {
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struct {
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/* Medium updates */
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uint32_t dcc_change:1;
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uint32_t color_space_change:1;
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uint32_t horizontal_mirror_change:1;
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uint32_t per_pixel_alpha_change:1;
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uint32_t rotation_change:1;
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uint32_t swizzle_change:1;
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uint32_t scaling_change:1;
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uint32_t position_change:1;
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uint32_t in_transfer_func_change:1;
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uint32_t input_csc_change:1;
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uint32_t coeff_reduction_change:1;
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uint32_t output_tf_change:1;
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uint32_t pixel_format_change:1;
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/* Full updates */
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uint32_t new_plane:1;
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uint32_t bpp_change:1;
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uint32_t gamma_change:1;
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uint32_t bandwidth_change:1;
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uint32_t clock_change:1;
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uint32_t stereo_format_change:1;
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uint32_t full_update:1;
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} bits;
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uint32_t raw;
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};
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struct dc_plane_state {
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struct dc_plane_address address;
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struct dc_plane_flip_time time;
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struct scaling_taps scaling_quality;
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struct rect src_rect;
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struct rect dst_rect;
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struct rect clip_rect;
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union plane_size plane_size;
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union dc_tiling_info tiling_info;
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struct dc_plane_dcc_param dcc;
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struct dc_gamma *gamma_correction;
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struct dc_transfer_func *in_transfer_func;
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struct dc_bias_and_scale *bias_and_scale;
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struct dc_csc_transform input_csc_color_matrix;
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struct fixed31_32 coeff_reduction_factor;
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uint32_t sdr_white_level;
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// TODO: No longer used, remove
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struct dc_hdr_static_metadata hdr_static_ctx;
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enum dc_color_space color_space;
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enum surface_pixel_format format;
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enum dc_rotation_angle rotation;
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enum plane_stereo_format stereo_format;
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bool is_tiling_rotated;
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bool per_pixel_alpha;
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bool visible;
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bool flip_immediate;
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bool horizontal_mirror;
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union surface_update_flags update_flags;
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/* private to DC core */
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struct dc_plane_status status;
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struct dc_context *ctx;
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/* HACK: Workaround for forcing full reprogramming under some conditions */
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bool force_full_update;
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/* private to dc_surface.c */
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enum dc_irq_source irq_source;
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struct kref refcount;
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};
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struct dc_plane_info {
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union plane_size plane_size;
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union dc_tiling_info tiling_info;
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struct dc_plane_dcc_param dcc;
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enum surface_pixel_format format;
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enum dc_rotation_angle rotation;
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enum plane_stereo_format stereo_format;
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enum dc_color_space color_space;
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unsigned int sdr_white_level;
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bool horizontal_mirror;
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bool visible;
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bool per_pixel_alpha;
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bool input_csc_enabled;
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};
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struct dc_scaling_info {
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struct rect src_rect;
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struct rect dst_rect;
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struct rect clip_rect;
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struct scaling_taps scaling_quality;
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};
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struct dc_surface_update {
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struct dc_plane_state *surface;
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|
|
|
/* isr safe update parameters. null means no updates */
|
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const struct dc_flip_addrs *flip_addr;
|
|
const struct dc_plane_info *plane_info;
|
|
const struct dc_scaling_info *scaling_info;
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|
|
|
/* following updates require alloc/sleep/spin that is not isr safe,
|
|
* null means no updates
|
|
*/
|
|
const struct dc_gamma *gamma;
|
|
const struct dc_transfer_func *in_transfer_func;
|
|
|
|
const struct dc_csc_transform *input_csc_color_matrix;
|
|
const struct fixed31_32 *coeff_reduction_factor;
|
|
};
|
|
|
|
/*
|
|
* Create a new surface with default parameters;
|
|
*/
|
|
struct dc_plane_state *dc_create_plane_state(struct dc *dc);
|
|
const struct dc_plane_status *dc_plane_get_status(
|
|
const struct dc_plane_state *plane_state);
|
|
|
|
void dc_plane_state_retain(struct dc_plane_state *plane_state);
|
|
void dc_plane_state_release(struct dc_plane_state *plane_state);
|
|
|
|
void dc_gamma_retain(struct dc_gamma *dc_gamma);
|
|
void dc_gamma_release(struct dc_gamma **dc_gamma);
|
|
struct dc_gamma *dc_create_gamma(void);
|
|
|
|
void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
|
|
void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
|
|
struct dc_transfer_func *dc_create_transfer_func(void);
|
|
|
|
/*
|
|
* This structure holds a surface address. There could be multiple addresses
|
|
* in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
|
|
* as frame durations and DCC format can also be set.
|
|
*/
|
|
struct dc_flip_addrs {
|
|
struct dc_plane_address address;
|
|
unsigned int flip_timestamp_in_us;
|
|
bool flip_immediate;
|
|
/* TODO: add flip duration for FreeSync */
|
|
};
|
|
|
|
bool dc_post_update_surfaces_to_stream(
|
|
struct dc *dc);
|
|
|
|
#include "dc_stream.h"
|
|
|
|
/*
|
|
* Structure to store surface/stream associations for validation
|
|
*/
|
|
struct dc_validation_set {
|
|
struct dc_stream_state *stream;
|
|
struct dc_plane_state *plane_states[MAX_SURFACES];
|
|
uint8_t plane_count;
|
|
};
|
|
|
|
enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
|
|
|
|
enum dc_status dc_validate_global_state(
|
|
struct dc *dc,
|
|
struct dc_state *new_ctx);
|
|
|
|
|
|
void dc_resource_state_construct(
|
|
const struct dc *dc,
|
|
struct dc_state *dst_ctx);
|
|
|
|
void dc_resource_state_copy_construct(
|
|
const struct dc_state *src_ctx,
|
|
struct dc_state *dst_ctx);
|
|
|
|
void dc_resource_state_copy_construct_current(
|
|
const struct dc *dc,
|
|
struct dc_state *dst_ctx);
|
|
|
|
void dc_resource_state_destruct(struct dc_state *context);
|
|
|
|
/*
|
|
* TODO update to make it about validation sets
|
|
* Set up streams and links associated to drive sinks
|
|
* The streams parameter is an absolute set of all active streams.
|
|
*
|
|
* After this call:
|
|
* Phy, Encoder, Timing Generator are programmed and enabled.
|
|
* New streams are enabled with blank stream; no memory read.
|
|
*/
|
|
bool dc_commit_state(struct dc *dc, struct dc_state *context);
|
|
|
|
|
|
struct dc_state *dc_create_state(void);
|
|
void dc_retain_state(struct dc_state *context);
|
|
void dc_release_state(struct dc_state *context);
|
|
|
|
/*******************************************************************************
|
|
* Link Interfaces
|
|
******************************************************************************/
|
|
|
|
struct dpcd_caps {
|
|
union dpcd_rev dpcd_rev;
|
|
union max_lane_count max_ln_count;
|
|
union max_down_spread max_down_spread;
|
|
|
|
/* dongle type (DP converter, CV smart dongle) */
|
|
enum display_dongle_type dongle_type;
|
|
/* Dongle's downstream count. */
|
|
union sink_count sink_count;
|
|
/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
|
|
indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
|
|
struct dc_dongle_caps dongle_caps;
|
|
|
|
uint32_t sink_dev_id;
|
|
int8_t sink_dev_id_str[6];
|
|
int8_t sink_hw_revision;
|
|
int8_t sink_fw_revision[2];
|
|
|
|
uint32_t branch_dev_id;
|
|
int8_t branch_dev_name[6];
|
|
int8_t branch_hw_revision;
|
|
int8_t branch_fw_revision[2];
|
|
|
|
bool allow_invalid_MSA_timing_param;
|
|
bool panel_mode_edp;
|
|
bool dpcd_display_control_capable;
|
|
};
|
|
|
|
#include "dc_link.h"
|
|
|
|
/*******************************************************************************
|
|
* Sink Interfaces - A sink corresponds to a display output device
|
|
******************************************************************************/
|
|
|
|
struct dc_container_id {
|
|
// 128bit GUID in binary form
|
|
unsigned char guid[16];
|
|
// 8 byte port ID -> ELD.PortID
|
|
unsigned int portId[2];
|
|
// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
|
|
unsigned short manufacturerName;
|
|
// 2 byte product code -> ELD.ProductCode
|
|
unsigned short productCode;
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
* The sink structure contains EDID and other display device properties
|
|
*/
|
|
struct dc_sink {
|
|
enum signal_type sink_signal;
|
|
struct dc_edid dc_edid; /* raw edid */
|
|
struct dc_edid_caps edid_caps; /* parse display caps */
|
|
struct dc_container_id *dc_container_id;
|
|
uint32_t dongle_max_pix_clk;
|
|
void *priv;
|
|
struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
|
|
bool converter_disable_audio;
|
|
|
|
/* private to DC core */
|
|
struct dc_link *link;
|
|
struct dc_context *ctx;
|
|
|
|
uint32_t sink_id;
|
|
|
|
/* private to dc_sink.c */
|
|
// refcount must be the last member in dc_sink, since we want the
|
|
// sink structure to be logically cloneable up to (but not including)
|
|
// refcount
|
|
struct kref refcount;
|
|
};
|
|
|
|
void dc_sink_retain(struct dc_sink *sink);
|
|
void dc_sink_release(struct dc_sink *sink);
|
|
|
|
struct dc_sink_init_data {
|
|
enum signal_type sink_signal;
|
|
struct dc_link *link;
|
|
uint32_t dongle_max_pix_clk;
|
|
bool converter_disable_audio;
|
|
};
|
|
|
|
struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
|
|
|
|
/* Newer interfaces */
|
|
struct dc_cursor {
|
|
struct dc_plane_address address;
|
|
struct dc_cursor_attributes attributes;
|
|
};
|
|
|
|
|
|
/*******************************************************************************
|
|
* Interrupt interfaces
|
|
******************************************************************************/
|
|
enum dc_irq_source dc_interrupt_to_irq_source(
|
|
struct dc *dc,
|
|
uint32_t src_id,
|
|
uint32_t ext_id);
|
|
bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
|
|
void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
|
|
enum dc_irq_source dc_get_hpd_irq_source_at_index(
|
|
struct dc *dc, uint32_t link_index);
|
|
|
|
/*******************************************************************************
|
|
* Power Interfaces
|
|
******************************************************************************/
|
|
|
|
void dc_set_power_state(
|
|
struct dc *dc,
|
|
enum dc_acpi_cm_power_state power_state);
|
|
void dc_resume(struct dc *dc);
|
|
|
|
#endif /* DC_INTERFACE_H_ */
|