187 lines
6.1 KiB
C
187 lines
6.1 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMD_SHARED_H__
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#define __AMD_SHARED_H__
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#include <drm/amd_asic_type.h>
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#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
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/*
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* Chip flags
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*/
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enum amd_chip_flags {
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AMD_ASIC_MASK = 0x0000ffffUL,
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AMD_FLAGS_MASK = 0xffff0000UL,
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AMD_IS_MOBILITY = 0x00010000UL,
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AMD_IS_APU = 0x00020000UL,
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AMD_IS_PX = 0x00040000UL,
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AMD_EXP_HW_SUPPORT = 0x00080000UL,
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};
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enum amd_ip_block_type {
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AMD_IP_BLOCK_TYPE_COMMON,
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AMD_IP_BLOCK_TYPE_GMC,
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AMD_IP_BLOCK_TYPE_IH,
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AMD_IP_BLOCK_TYPE_SMC,
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AMD_IP_BLOCK_TYPE_PSP,
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AMD_IP_BLOCK_TYPE_DCE,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_IP_BLOCK_TYPE_SDMA,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_IP_BLOCK_TYPE_ACP,
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AMD_IP_BLOCK_TYPE_VCN
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};
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enum amd_clockgating_state {
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AMD_CG_STATE_GATE = 0,
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AMD_CG_STATE_UNGATE,
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};
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enum amd_powergating_state {
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AMD_PG_STATE_GATE = 0,
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AMD_PG_STATE_UNGATE,
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};
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/* CG flags */
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#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
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#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
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#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
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#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
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#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
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#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
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#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
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#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
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#define AMD_CG_SUPPORT_MC_LS (1 << 8)
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#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
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#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
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#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
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#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
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#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
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#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
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#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
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#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
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#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
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#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
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#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
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#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
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#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
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#define AMD_CG_SUPPORT_DRM_MGCG (1 << 22)
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#define AMD_CG_SUPPORT_DF_MGCG (1 << 23)
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#define AMD_CG_SUPPORT_VCN_MGCG (1 << 24)
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/* PG flags */
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#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
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#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
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#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
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#define AMD_PG_SUPPORT_UVD (1 << 3)
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#define AMD_PG_SUPPORT_VCE (1 << 4)
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#define AMD_PG_SUPPORT_CP (1 << 5)
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#define AMD_PG_SUPPORT_GDS (1 << 6)
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#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
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#define AMD_PG_SUPPORT_SDMA (1 << 8)
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#define AMD_PG_SUPPORT_ACP (1 << 9)
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#define AMD_PG_SUPPORT_SAMU (1 << 10)
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#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
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#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
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#define AMD_PG_SUPPORT_MMHUB (1 << 13)
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#define AMD_PG_SUPPORT_VCN (1 << 14)
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enum PP_FEATURE_MASK {
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PP_SCLK_DPM_MASK = 0x1,
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PP_MCLK_DPM_MASK = 0x2,
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PP_PCIE_DPM_MASK = 0x4,
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PP_SCLK_DEEP_SLEEP_MASK = 0x8,
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PP_POWER_CONTAINMENT_MASK = 0x10,
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PP_UVD_HANDSHAKE_MASK = 0x20,
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PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
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PP_VBI_TIME_SUPPORT_MASK = 0x80,
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PP_ULV_MASK = 0x100,
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PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
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PP_CLOCK_STRETCH_MASK = 0x400,
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PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
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PP_SOCCLK_DPM_MASK = 0x1000,
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PP_DCEFCLK_DPM_MASK = 0x2000,
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PP_OVERDRIVE_MASK = 0x4000,
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PP_GFXOFF_MASK = 0x8000,
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PP_ACG_MASK = 0x10000,
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PP_STUTTER_MODE = 0x20000,
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};
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/**
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* struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
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*/
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struct amd_ip_funcs {
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/** @name: Name of IP block */
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char *name;
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/**
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* @early_init:
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*
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* sets up early driver state (pre sw_init),
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* does not configure hw - Optional
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*/
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int (*early_init)(void *handle);
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/** @late_init: sets up late driver/hw state (post hw_init) - Optional */
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int (*late_init)(void *handle);
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/** @sw_init: sets up driver state, does not configure hw */
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int (*sw_init)(void *handle);
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/** @sw_fini: tears down driver state, does not configure hw */
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int (*sw_fini)(void *handle);
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/** @hw_init: sets up the hw state */
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int (*hw_init)(void *handle);
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/** @hw_fini: tears down the hw state */
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int (*hw_fini)(void *handle);
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/** @late_fini: final cleanup */
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void (*late_fini)(void *handle);
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/** @suspend: handles IP specific hw/sw changes for suspend */
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int (*suspend)(void *handle);
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/** @resume: handles IP specific hw/sw changes for resume */
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int (*resume)(void *handle);
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/** @is_idle: returns current IP block idle status */
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bool (*is_idle)(void *handle);
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/** @wait_for_idle: poll for idle */
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int (*wait_for_idle)(void *handle);
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/** @check_soft_reset: check soft reset the IP block */
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bool (*check_soft_reset)(void *handle);
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/** @pre_soft_reset: pre soft reset the IP block */
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int (*pre_soft_reset)(void *handle);
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/** @soft_reset: soft reset the IP block */
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int (*soft_reset)(void *handle);
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/** @post_soft_reset: post soft reset the IP block */
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int (*post_soft_reset)(void *handle);
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/** @set_clockgating_state: enable/disable cg for the IP block */
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int (*set_clockgating_state)(void *handle,
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enum amd_clockgating_state state);
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/** @set_powergating_state: enable/disable pg for the IP block */
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int (*set_powergating_state)(void *handle,
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enum amd_powergating_state state);
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/** @get_clockgating_state: get current clockgating status */
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void (*get_clockgating_state)(void *handle, u32 *flags);
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};
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#endif /* __AMD_SHARED_H__ */
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