552 lines
12 KiB
C
552 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Etnaviv Project
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* Copyright (C) 2017 Zodiac Inflight Innovations
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*/
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#include "common.xml.h"
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#include "etnaviv_gpu.h"
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#include "etnaviv_perfmon.h"
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#include "state_hi.xml.h"
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struct etnaviv_pm_domain;
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struct etnaviv_pm_signal {
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char name[64];
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u32 data;
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u32 (*sample)(struct etnaviv_gpu *gpu,
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const struct etnaviv_pm_domain *domain,
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const struct etnaviv_pm_signal *signal);
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};
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struct etnaviv_pm_domain {
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char name[64];
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/* profile register */
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u32 profile_read;
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u32 profile_config;
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u8 nr_signals;
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const struct etnaviv_pm_signal *signal;
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};
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struct etnaviv_pm_domain_meta {
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unsigned int feature;
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const struct etnaviv_pm_domain *domains;
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u32 nr_domains;
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};
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static u32 perf_reg_read(struct etnaviv_gpu *gpu,
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const struct etnaviv_pm_domain *domain,
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const struct etnaviv_pm_signal *signal)
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{
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gpu_write(gpu, domain->profile_config, signal->data);
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return gpu_read(gpu, domain->profile_read);
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}
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static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
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const struct etnaviv_pm_domain *domain,
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const struct etnaviv_pm_signal *signal)
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{
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u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
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u32 value = 0;
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unsigned i;
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for (i = 0; i < gpu->identity.pixel_pipes; i++) {
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clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
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clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i);
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gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
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gpu_write(gpu, domain->profile_config, signal->data);
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value += gpu_read(gpu, domain->profile_read);
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}
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/* switch back to pixel pipe 0 to prevent GPU hang */
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clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
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clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0);
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gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
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return value;
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}
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static u32 hi_total_cycle_read(struct etnaviv_gpu *gpu,
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const struct etnaviv_pm_domain *domain,
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const struct etnaviv_pm_signal *signal)
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{
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u32 reg = VIVS_HI_PROFILE_TOTAL_CYCLES;
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if (gpu->identity.model == chipModel_GC880 ||
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gpu->identity.model == chipModel_GC2000 ||
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gpu->identity.model == chipModel_GC2100)
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reg = VIVS_MC_PROFILE_CYCLE_COUNTER;
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return gpu_read(gpu, reg);
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}
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static u32 hi_total_idle_cycle_read(struct etnaviv_gpu *gpu,
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const struct etnaviv_pm_domain *domain,
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const struct etnaviv_pm_signal *signal)
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{
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u32 reg = VIVS_HI_PROFILE_IDLE_CYCLES;
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if (gpu->identity.model == chipModel_GC880 ||
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gpu->identity.model == chipModel_GC2000 ||
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gpu->identity.model == chipModel_GC2100)
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reg = VIVS_HI_PROFILE_TOTAL_CYCLES;
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return gpu_read(gpu, reg);
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}
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static const struct etnaviv_pm_domain doms_3d[] = {
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{
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.name = "HI",
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.profile_read = VIVS_MC_PROFILE_HI_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG2,
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.nr_signals = 5,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"TOTAL_CYCLES",
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0,
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&hi_total_cycle_read
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},
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{
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"IDLE_CYCLES",
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0,
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&hi_total_idle_cycle_read
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},
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{
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"AXI_CYCLES_READ_REQUEST_STALLED",
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VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED,
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&perf_reg_read
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},
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{
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"AXI_CYCLES_WRITE_REQUEST_STALLED",
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VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED,
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&perf_reg_read
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},
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{
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"AXI_CYCLES_WRITE_DATA_STALLED",
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VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED,
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&perf_reg_read
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}
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}
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},
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{
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.name = "PE",
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.profile_read = VIVS_MC_PROFILE_PE_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG0,
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.nr_signals = 4,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"PIXEL_COUNT_KILLED_BY_COLOR_PIPE",
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VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE,
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&pipe_reg_read
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},
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{
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"PIXEL_COUNT_KILLED_BY_DEPTH_PIPE",
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VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE,
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&pipe_reg_read
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},
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{
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"PIXEL_COUNT_DRAWN_BY_COLOR_PIPE",
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VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE,
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&pipe_reg_read
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},
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{
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"PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE",
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VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE,
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&pipe_reg_read
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}
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}
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},
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{
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.name = "SH",
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.profile_read = VIVS_MC_PROFILE_SH_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG0,
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.nr_signals = 9,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"SHADER_CYCLES",
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VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES,
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&perf_reg_read
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},
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{
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"PS_INST_COUNTER",
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VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER,
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&perf_reg_read
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},
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{
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"RENDERED_PIXEL_COUNTER",
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VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER,
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&perf_reg_read
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},
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{
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"VS_INST_COUNTER",
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VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER,
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&pipe_reg_read
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},
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{
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"RENDERED_VERTICE_COUNTER",
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VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER,
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&pipe_reg_read
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},
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{
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"VTX_BRANCH_INST_COUNTER",
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VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER,
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&pipe_reg_read
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},
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{
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"VTX_TEXLD_INST_COUNTER",
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VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER,
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&pipe_reg_read
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},
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{
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"PXL_BRANCH_INST_COUNTER",
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VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER,
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&pipe_reg_read
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},
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{
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"PXL_TEXLD_INST_COUNTER",
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VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER,
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&pipe_reg_read
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}
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}
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},
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{
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.name = "PA",
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.profile_read = VIVS_MC_PROFILE_PA_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG1,
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.nr_signals = 6,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"INPUT_VTX_COUNTER",
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VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER,
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&perf_reg_read
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},
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{
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"INPUT_PRIM_COUNTER",
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VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER,
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&perf_reg_read
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},
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{
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"OUTPUT_PRIM_COUNTER",
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VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER,
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&perf_reg_read
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},
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{
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"DEPTH_CLIPPED_COUNTER",
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VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER,
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&pipe_reg_read
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},
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{
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"TRIVIAL_REJECTED_COUNTER",
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VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER,
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&pipe_reg_read
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},
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{
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"CULLED_COUNTER",
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VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER,
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&pipe_reg_read
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}
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}
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},
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{
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.name = "SE",
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.profile_read = VIVS_MC_PROFILE_SE_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG1,
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.nr_signals = 2,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"CULLED_TRIANGLE_COUNT",
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VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT,
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&perf_reg_read
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},
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{
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"CULLED_LINES_COUNT",
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VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT,
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&perf_reg_read
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}
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}
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},
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{
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.name = "RA",
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.profile_read = VIVS_MC_PROFILE_RA_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG1,
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.nr_signals = 7,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"VALID_PIXEL_COUNT",
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VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT,
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&perf_reg_read
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},
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{
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"TOTAL_QUAD_COUNT",
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VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT,
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&perf_reg_read
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},
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{
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"VALID_QUAD_COUNT_AFTER_EARLY_Z",
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VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z,
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&perf_reg_read
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},
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{
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"TOTAL_PRIMITIVE_COUNT",
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VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT,
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&perf_reg_read
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},
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{
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"PIPE_CACHE_MISS_COUNTER",
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VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER,
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&perf_reg_read
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},
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{
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"PREFETCH_CACHE_MISS_COUNTER",
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VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER,
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&perf_reg_read
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},
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{
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"CULLED_QUAD_COUNT",
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VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT,
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&perf_reg_read
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}
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}
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},
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{
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.name = "TX",
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.profile_read = VIVS_MC_PROFILE_TX_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG1,
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.nr_signals = 9,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"TOTAL_BILINEAR_REQUESTS",
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VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS,
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&perf_reg_read
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},
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{
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"TOTAL_TRILINEAR_REQUESTS",
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VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS,
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&perf_reg_read
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},
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{
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"TOTAL_DISCARDED_TEXTURE_REQUESTS",
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VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS,
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&perf_reg_read
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},
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{
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"TOTAL_TEXTURE_REQUESTS",
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VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS,
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&perf_reg_read
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},
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{
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"MEM_READ_COUNT",
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VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT,
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&perf_reg_read
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},
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{
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"MEM_READ_IN_8B_COUNT",
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VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT,
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&perf_reg_read
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},
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{
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"CACHE_MISS_COUNT",
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VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT,
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&perf_reg_read
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},
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{
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"CACHE_HIT_TEXEL_COUNT",
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VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT,
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&perf_reg_read
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},
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{
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"CACHE_MISS_TEXEL_COUNT",
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VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT,
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&perf_reg_read
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}
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}
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},
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{
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.name = "MC",
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.profile_read = VIVS_MC_PROFILE_MC_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG2,
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.nr_signals = 3,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"TOTAL_READ_REQ_8B_FROM_PIPELINE",
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VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE,
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&perf_reg_read
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},
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{
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"TOTAL_READ_REQ_8B_FROM_IP",
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VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP,
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&perf_reg_read
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},
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{
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"TOTAL_WRITE_REQ_8B_FROM_PIPELINE",
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VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE,
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&perf_reg_read
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}
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}
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}
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};
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static const struct etnaviv_pm_domain doms_2d[] = {
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{
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.name = "PE",
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.profile_read = VIVS_MC_PROFILE_PE_READ,
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.profile_config = VIVS_MC_PROFILE_CONFIG0,
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.nr_signals = 1,
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.signal = (const struct etnaviv_pm_signal[]) {
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{
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"PIXELS_RENDERED_2D",
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VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D,
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&pipe_reg_read
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}
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}
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}
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};
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static const struct etnaviv_pm_domain doms_vg[] = {
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};
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static const struct etnaviv_pm_domain_meta doms_meta[] = {
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{
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.feature = chipFeatures_PIPE_3D,
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.nr_domains = ARRAY_SIZE(doms_3d),
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.domains = &doms_3d[0]
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},
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{
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.feature = chipFeatures_PIPE_2D,
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.nr_domains = ARRAY_SIZE(doms_2d),
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.domains = &doms_2d[0]
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},
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{
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.feature = chipFeatures_PIPE_VG,
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.nr_domains = ARRAY_SIZE(doms_vg),
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.domains = &doms_vg[0]
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}
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};
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static unsigned int num_pm_domains(const struct etnaviv_gpu *gpu)
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{
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unsigned int num = 0, i;
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for (i = 0; i < ARRAY_SIZE(doms_meta); i++) {
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const struct etnaviv_pm_domain_meta *meta = &doms_meta[i];
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if (gpu->identity.features & meta->feature)
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num += meta->nr_domains;
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}
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return num;
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}
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static const struct etnaviv_pm_domain *pm_domain(const struct etnaviv_gpu *gpu,
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unsigned int index)
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{
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const struct etnaviv_pm_domain *domain = NULL;
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unsigned int offset = 0, i;
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for (i = 0; i < ARRAY_SIZE(doms_meta); i++) {
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const struct etnaviv_pm_domain_meta *meta = &doms_meta[i];
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if (!(gpu->identity.features & meta->feature))
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continue;
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if (index - offset >= meta->nr_domains) {
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offset += meta->nr_domains;
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continue;
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}
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domain = meta->domains + (index - offset);
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}
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return domain;
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}
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int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
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struct drm_etnaviv_pm_domain *domain)
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{
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const unsigned int nr_domains = num_pm_domains(gpu);
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const struct etnaviv_pm_domain *dom;
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if (domain->iter >= nr_domains)
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return -EINVAL;
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dom = pm_domain(gpu, domain->iter);
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if (!dom)
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return -EINVAL;
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domain->id = domain->iter;
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domain->nr_signals = dom->nr_signals;
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strncpy(domain->name, dom->name, sizeof(domain->name));
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domain->iter++;
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if (domain->iter == nr_domains)
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domain->iter = 0xff;
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return 0;
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}
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int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
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struct drm_etnaviv_pm_signal *signal)
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{
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const unsigned int nr_domains = num_pm_domains(gpu);
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const struct etnaviv_pm_domain *dom;
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const struct etnaviv_pm_signal *sig;
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if (signal->domain >= nr_domains)
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return -EINVAL;
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dom = pm_domain(gpu, signal->domain);
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if (!dom)
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return -EINVAL;
|
|
|
|
if (signal->iter >= dom->nr_signals)
|
|
return -EINVAL;
|
|
|
|
sig = &dom->signal[signal->iter];
|
|
|
|
signal->id = signal->iter;
|
|
strncpy(signal->name, sig->name, sizeof(signal->name));
|
|
|
|
signal->iter++;
|
|
if (signal->iter == dom->nr_signals)
|
|
signal->iter = 0xffff;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int etnaviv_pm_req_validate(const struct drm_etnaviv_gem_submit_pmr *r,
|
|
u32 exec_state)
|
|
{
|
|
const struct etnaviv_pm_domain_meta *meta = &doms_meta[exec_state];
|
|
const struct etnaviv_pm_domain *dom;
|
|
|
|
if (r->domain >= meta->nr_domains)
|
|
return -EINVAL;
|
|
|
|
dom = meta->domains + r->domain;
|
|
|
|
if (r->signal >= dom->nr_signals)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
|
|
const struct etnaviv_perfmon_request *pmr, u32 exec_state)
|
|
{
|
|
const struct etnaviv_pm_domain_meta *meta = &doms_meta[exec_state];
|
|
const struct etnaviv_pm_domain *dom;
|
|
const struct etnaviv_pm_signal *sig;
|
|
u32 *bo = pmr->bo_vma;
|
|
u32 val;
|
|
|
|
dom = meta->domains + pmr->domain;
|
|
sig = &dom->signal[pmr->signal];
|
|
val = sig->sample(gpu, dom, sig);
|
|
|
|
*(bo + pmr->offset) = val;
|
|
}
|