223 lines
7.2 KiB
C
223 lines
7.2 KiB
C
/*
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* Broadcom NetXtreme-E RoCE driver.
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*
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* Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
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* Broadcom refers to Broadcom Limited and/or its subsidiaries.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* BSD license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Description: RDMA Controller HW interface (header)
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*/
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#ifndef __BNXT_QPLIB_RCFW_H__
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#define __BNXT_QPLIB_RCFW_H__
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#define RCFW_CMDQ_TRIG_VAL 1
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#define RCFW_COMM_PCI_BAR_REGION 0
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#define RCFW_COMM_CONS_PCI_BAR_REGION 2
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#define RCFW_COMM_BASE_OFFSET 0x600
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#define RCFW_PF_COMM_PROD_OFFSET 0xc
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#define RCFW_VF_COMM_PROD_OFFSET 0xc
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#define RCFW_COMM_TRIG_OFFSET 0x100
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#define RCFW_COMM_SIZE 0x104
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#define RCFW_DBR_PCI_BAR_REGION 2
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#define RCFW_DBR_BASE_PAGE_SHIFT 12
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#define RCFW_CMD_PREP(req, CMD, cmd_flags) \
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do { \
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memset(&(req), 0, sizeof((req))); \
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(req).opcode = CMDQ_BASE_OPCODE_##CMD; \
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(req).cmd_size = (sizeof((req)) + \
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BNXT_QPLIB_CMDQE_UNITS - 1) / \
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BNXT_QPLIB_CMDQE_UNITS; \
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(req).flags = cpu_to_le16(cmd_flags); \
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} while (0)
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#define RCFW_CMD_WAIT_TIME_MS 20000 /* 20 Seconds timeout */
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/* CMDQ elements */
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#define BNXT_QPLIB_CMDQE_MAX_CNT 256
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#define BNXT_QPLIB_CMDQE_UNITS sizeof(struct bnxt_qplib_cmdqe)
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#define BNXT_QPLIB_CMDQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CMDQE_UNITS)
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#define MAX_CMDQ_IDX (BNXT_QPLIB_CMDQE_MAX_CNT - 1)
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#define MAX_CMDQ_IDX_PER_PG (BNXT_QPLIB_CMDQE_CNT_PER_PG - 1)
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#define RCFW_MAX_OUTSTANDING_CMD BNXT_QPLIB_CMDQE_MAX_CNT
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#define RCFW_MAX_COOKIE_VALUE 0x7FFF
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#define RCFW_CMD_IS_BLOCKING 0x8000
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#define RCFW_BLOCKED_CMD_WAIT_COUNT 0x4E20
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/* Cmdq contains a fix number of a 16-Byte slots */
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struct bnxt_qplib_cmdqe {
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u8 data[16];
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};
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static inline u32 get_cmdq_pg(u32 val)
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{
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return (val & ~MAX_CMDQ_IDX_PER_PG) / BNXT_QPLIB_CMDQE_CNT_PER_PG;
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}
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static inline u32 get_cmdq_idx(u32 val)
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{
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return val & MAX_CMDQ_IDX_PER_PG;
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}
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/* Crsq buf is 1024-Byte */
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struct bnxt_qplib_crsbe {
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u8 data[1024];
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};
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/* CREQ */
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/* Allocate 1 per QP for async error notification for now */
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#define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024)
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#define BNXT_QPLIB_CREQE_UNITS 16 /* 16-Bytes per prod unit */
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#define BNXT_QPLIB_CREQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
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#define MAX_CREQ_IDX (BNXT_QPLIB_CREQE_MAX_CNT - 1)
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#define MAX_CREQ_IDX_PER_PG (BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
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static inline u32 get_creq_pg(u32 val)
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{
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return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
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}
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static inline u32 get_creq_idx(u32 val)
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{
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return val & MAX_CREQ_IDX_PER_PG;
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}
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#define BNXT_QPLIB_CREQE_PER_PG (PAGE_SIZE / sizeof(struct creq_base))
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#define CREQ_CMP_VALID(hdr, raw_cons, cp_bit) \
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(!!((hdr)->v & CREQ_BASE_V) == \
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!((raw_cons) & (cp_bit)))
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#define CREQ_DB_KEY_CP (0x2 << CMPL_DOORBELL_KEY_SFT)
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#define CREQ_DB_IDX_VALID CMPL_DOORBELL_IDX_VALID
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#define CREQ_DB_IRQ_DIS CMPL_DOORBELL_MASK
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#define CREQ_DB_CP_FLAGS_REARM (CREQ_DB_KEY_CP | \
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CREQ_DB_IDX_VALID)
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#define CREQ_DB_CP_FLAGS (CREQ_DB_KEY_CP | \
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CREQ_DB_IDX_VALID | \
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CREQ_DB_IRQ_DIS)
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#define CREQ_DB_REARM(db, raw_cons, cp_bit) \
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writel(CREQ_DB_CP_FLAGS_REARM | ((raw_cons) & ((cp_bit) - 1)), db)
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#define CREQ_DB(db, raw_cons, cp_bit) \
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writel(CREQ_DB_CP_FLAGS | ((raw_cons) & ((cp_bit) - 1)), db)
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#define CREQ_ENTRY_POLL_BUDGET 0x100
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/* HWQ */
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struct bnxt_qplib_crsq {
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struct creq_qp_event *resp;
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u32 req_size;
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};
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struct bnxt_qplib_rcfw_sbuf {
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void *sb;
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dma_addr_t dma_addr;
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u32 size;
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};
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struct bnxt_qplib_qp_node {
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u32 qp_id; /* QP id */
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void *qp_handle; /* ptr to qplib_qp */
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};
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/* RCFW Communication Channels */
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struct bnxt_qplib_rcfw {
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struct pci_dev *pdev;
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int vector;
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struct tasklet_struct worker;
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bool requested;
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unsigned long *cmdq_bitmap;
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u32 bmap_size;
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unsigned long flags;
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#define FIRMWARE_INITIALIZED_FLAG 0
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#define FIRMWARE_FIRST_FLAG 31
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#define FIRMWARE_TIMED_OUT 3
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wait_queue_head_t waitq;
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int (*aeq_handler)(struct bnxt_qplib_rcfw *,
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void *, void *);
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u32 seq_num;
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/* Bar region info */
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void __iomem *cmdq_bar_reg_iomem;
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u16 cmdq_bar_reg;
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u16 cmdq_bar_reg_prod_off;
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u16 cmdq_bar_reg_trig_off;
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u16 creq_ring_id;
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u16 creq_bar_reg;
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void __iomem *creq_bar_reg_iomem;
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/* Cmd-Resp and Async Event notification queue */
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struct bnxt_qplib_hwq creq;
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u64 creq_qp_event_processed;
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u64 creq_func_event_processed;
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/* Actual Cmd and Resp Queues */
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struct bnxt_qplib_hwq cmdq;
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struct bnxt_qplib_crsq *crsqe_tbl;
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int qp_tbl_size;
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struct bnxt_qplib_qp_node *qp_tbl;
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};
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void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
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int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
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struct bnxt_qplib_rcfw *rcfw, int qp_tbl_sz);
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void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
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void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
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int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
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bool need_init);
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int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
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struct bnxt_qplib_rcfw *rcfw,
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int msix_vector,
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int cp_bar_reg_off, int virt_fn,
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int (*aeq_handler)(struct bnxt_qplib_rcfw *,
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void *aeqe, void *obj));
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struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
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struct bnxt_qplib_rcfw *rcfw,
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u32 size);
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void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
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struct bnxt_qplib_rcfw_sbuf *sbuf);
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int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
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struct cmdq_base *req, struct creq_base *resp,
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void *sbuf, u8 is_block);
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int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
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int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
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struct bnxt_qplib_ctx *ctx, int is_virtfn);
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void bnxt_qplib_mark_qp_error(void *qp_handle);
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#endif /* __BNXT_QPLIB_RCFW_H__ */
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