682 lines
18 KiB
C
682 lines
18 KiB
C
/* $Id: isac.c,v 1.31.2.3 2004/01/13 14:31:25 keil Exp $
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*
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* ISAC specific routines
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*
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* Author Karsten Keil
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* Copyright by Karsten Keil <keil@isdn4linux.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* For changes and modifications please read
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* Documentation/isdn/HiSax.cert
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*
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*/
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#include "hisax.h"
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#include "isac.h"
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#include "arcofi.h"
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#include "isdnl1.h"
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#define DBUSY_TIMER_VALUE 80
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#define ARCOFI_USE 1
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static char *ISACVer[] =
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{"2086/2186 V1.1", "2085 B1", "2085 B2",
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"2085 V2.3"};
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void ISACVersion(struct IsdnCardState *cs, char *s)
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{
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int val;
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val = cs->readisac(cs, ISAC_RBCH);
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printk(KERN_INFO "%s ISAC version (%x): %s\n", s, val, ISACVer[(val >> 5) & 3]);
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}
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static void
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ph_command(struct IsdnCardState *cs, unsigned int command)
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{
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ph_command %x", command);
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cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3);
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}
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static void
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isac_new_ph(struct IsdnCardState *cs)
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{
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switch (cs->dc.isac.ph_state) {
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case (ISAC_IND_RS):
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case (ISAC_IND_EI):
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ph_command(cs, ISAC_CMD_DUI);
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l1_msg(cs, HW_RESET | INDICATION, NULL);
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break;
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case (ISAC_IND_DID):
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l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
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break;
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case (ISAC_IND_DR):
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l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
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break;
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case (ISAC_IND_PU):
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l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
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break;
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case (ISAC_IND_RSY):
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l1_msg(cs, HW_RSYNC | INDICATION, NULL);
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break;
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case (ISAC_IND_ARD):
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l1_msg(cs, HW_INFO2 | INDICATION, NULL);
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break;
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case (ISAC_IND_AI8):
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l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
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break;
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case (ISAC_IND_AI10):
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l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
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break;
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default:
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break;
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}
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}
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static void
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isac_bh(struct work_struct *work)
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{
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struct IsdnCardState *cs =
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container_of(work, struct IsdnCardState, tqueue);
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struct PStack *stptr;
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if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
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if (cs->debug)
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debugl1(cs, "D-Channel Busy cleared");
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stptr = cs->stlist;
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while (stptr != NULL) {
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stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
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stptr = stptr->next;
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}
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}
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if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
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isac_new_ph(cs);
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if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
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DChannel_proc_rcv(cs);
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if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
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DChannel_proc_xmt(cs);
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#if ARCOFI_USE
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if (!test_bit(HW_ARCOFI, &cs->HW_Flags))
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return;
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if (test_and_clear_bit(D_RX_MON1, &cs->event))
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arcofi_fsm(cs, ARCOFI_RX_END, NULL);
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if (test_and_clear_bit(D_TX_MON1, &cs->event))
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arcofi_fsm(cs, ARCOFI_TX_END, NULL);
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#endif
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}
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static void
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isac_empty_fifo(struct IsdnCardState *cs, int count)
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{
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u_char *ptr;
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "isac_empty_fifo");
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if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "isac_empty_fifo overrun %d",
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cs->rcvidx + count);
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cs->writeisac(cs, ISAC_CMDR, 0x80);
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cs->rcvidx = 0;
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return;
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}
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ptr = cs->rcvbuf + cs->rcvidx;
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cs->rcvidx += count;
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cs->readisacfifo(cs, ptr, count);
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cs->writeisac(cs, ISAC_CMDR, 0x80);
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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char *t = cs->dlog;
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t += sprintf(t, "isac_empty_fifo cnt %d", count);
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QuickHex(t, ptr, count);
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debugl1(cs, "%s", cs->dlog);
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}
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}
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static void
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isac_fill_fifo(struct IsdnCardState *cs)
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{
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int count, more;
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u_char *ptr;
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "isac_fill_fifo");
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if (!cs->tx_skb)
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return;
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count = cs->tx_skb->len;
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if (count <= 0)
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return;
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more = 0;
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if (count > 32) {
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more = !0;
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count = 32;
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}
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ptr = cs->tx_skb->data;
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skb_pull(cs->tx_skb, count);
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cs->tx_cnt += count;
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cs->writeisacfifo(cs, ptr, count);
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cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);
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if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
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debugl1(cs, "isac_fill_fifo dbusytimer running");
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del_timer(&cs->dbusytimer);
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}
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cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
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add_timer(&cs->dbusytimer);
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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char *t = cs->dlog;
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t += sprintf(t, "isac_fill_fifo cnt %d", count);
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QuickHex(t, ptr, count);
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debugl1(cs, "%s", cs->dlog);
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}
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}
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void
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isac_interrupt(struct IsdnCardState *cs, u_char val)
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{
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u_char exval, v1;
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struct sk_buff *skb;
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unsigned int count;
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ISAC interrupt %x", val);
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if (val & 0x80) { /* RME */
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exval = cs->readisac(cs, ISAC_RSTA);
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if ((exval & 0x70) != 0x20) {
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if (exval & 0x40) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC RDO");
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#ifdef ERROR_STATISTIC
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cs->err_rx++;
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#endif
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}
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if (!(exval & 0x20)) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC CRC error");
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#ifdef ERROR_STATISTIC
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cs->err_crc++;
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#endif
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}
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cs->writeisac(cs, ISAC_CMDR, 0x80);
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} else {
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count = cs->readisac(cs, ISAC_RBCL) & 0x1f;
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if (count == 0)
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count = 32;
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isac_empty_fifo(cs, count);
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count = cs->rcvidx;
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if (count > 0) {
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cs->rcvidx = 0;
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skb = alloc_skb(count, GFP_ATOMIC);
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if (!skb)
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printk(KERN_WARNING "HiSax: D receive out of memory\n");
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else {
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skb_put_data(skb, cs->rcvbuf, count);
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skb_queue_tail(&cs->rq, skb);
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}
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}
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}
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cs->rcvidx = 0;
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schedule_event(cs, D_RCVBUFREADY);
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}
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if (val & 0x40) { /* RPF */
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isac_empty_fifo(cs, 32);
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}
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if (val & 0x20) { /* RSC */
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/* never */
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC RSC interrupt");
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}
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if (val & 0x10) { /* XPR */
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if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
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del_timer(&cs->dbusytimer);
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if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
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schedule_event(cs, D_CLEARBUSY);
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if (cs->tx_skb) {
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if (cs->tx_skb->len) {
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isac_fill_fifo(cs);
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goto afterXPR;
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} else {
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dev_kfree_skb_irq(cs->tx_skb);
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cs->tx_cnt = 0;
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cs->tx_skb = NULL;
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}
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}
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cs->tx_skb = skb_dequeue(&cs->sq);
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if (cs->tx_skb) {
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cs->tx_cnt = 0;
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isac_fill_fifo(cs);
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} else
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schedule_event(cs, D_XMTBUFREADY);
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}
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afterXPR:
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if (val & 0x04) { /* CISQ */
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exval = cs->readisac(cs, ISAC_CIR0);
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ISAC CIR0 %02X", exval);
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if (exval & 2) {
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cs->dc.isac.ph_state = (exval >> 2) & 0xf;
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ph_state change %x", cs->dc.isac.ph_state);
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schedule_event(cs, D_L1STATECHANGE);
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}
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if (exval & 1) {
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exval = cs->readisac(cs, ISAC_CIR1);
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ISAC CIR1 %02X", exval);
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}
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}
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if (val & 0x02) { /* SIN */
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/* never */
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC SIN interrupt");
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}
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if (val & 0x01) { /* EXI */
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exval = cs->readisac(cs, ISAC_EXIR);
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC EXIR %02x", exval);
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if (exval & 0x80) { /* XMR */
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debugl1(cs, "ISAC XMR");
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printk(KERN_WARNING "HiSax: ISAC XMR\n");
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}
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if (exval & 0x40) { /* XDU */
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debugl1(cs, "ISAC XDU");
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printk(KERN_WARNING "HiSax: ISAC XDU\n");
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#ifdef ERROR_STATISTIC
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cs->err_tx++;
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#endif
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if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
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del_timer(&cs->dbusytimer);
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if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
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schedule_event(cs, D_CLEARBUSY);
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if (cs->tx_skb) { /* Restart frame */
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skb_push(cs->tx_skb, cs->tx_cnt);
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cs->tx_cnt = 0;
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isac_fill_fifo(cs);
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} else {
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printk(KERN_WARNING "HiSax: ISAC XDU no skb\n");
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debugl1(cs, "ISAC XDU no skb");
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}
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}
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if (exval & 0x04) { /* MOS */
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v1 = cs->readisac(cs, ISAC_MOSR);
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if (cs->debug & L1_DEB_MONITOR)
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debugl1(cs, "ISAC MOSR %02x", v1);
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#if ARCOFI_USE
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if (v1 & 0x08) {
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if (!cs->dc.isac.mon_rx) {
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cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
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if (!cs->dc.isac.mon_rx) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC MON RX out of memory!");
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cs->dc.isac.mocr &= 0xf0;
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cs->dc.isac.mocr |= 0x0a;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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goto afterMONR0;
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} else
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cs->dc.isac.mon_rxp = 0;
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}
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if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
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cs->dc.isac.mocr &= 0xf0;
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cs->dc.isac.mocr |= 0x0a;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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cs->dc.isac.mon_rxp = 0;
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC MON RX overflow!");
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goto afterMONR0;
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}
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cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR0);
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if (cs->debug & L1_DEB_MONITOR)
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debugl1(cs, "ISAC MOR0 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp - 1]);
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if (cs->dc.isac.mon_rxp == 1) {
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cs->dc.isac.mocr |= 0x04;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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}
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}
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afterMONR0:
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if (v1 & 0x80) {
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if (!cs->dc.isac.mon_rx) {
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cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
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if (!cs->dc.isac.mon_rx) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC MON RX out of memory!");
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cs->dc.isac.mocr &= 0x0f;
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cs->dc.isac.mocr |= 0xa0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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goto afterMONR1;
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} else
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cs->dc.isac.mon_rxp = 0;
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}
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if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
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cs->dc.isac.mocr &= 0x0f;
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cs->dc.isac.mocr |= 0xa0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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cs->dc.isac.mon_rxp = 0;
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "ISAC MON RX overflow!");
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goto afterMONR1;
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}
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cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR1);
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if (cs->debug & L1_DEB_MONITOR)
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debugl1(cs, "ISAC MOR1 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp - 1]);
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cs->dc.isac.mocr |= 0x40;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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}
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afterMONR1:
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if (v1 & 0x04) {
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cs->dc.isac.mocr &= 0xf0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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cs->dc.isac.mocr |= 0x0a;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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schedule_event(cs, D_RX_MON0);
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}
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if (v1 & 0x40) {
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cs->dc.isac.mocr &= 0x0f;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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cs->dc.isac.mocr |= 0xa0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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schedule_event(cs, D_RX_MON1);
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}
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if (v1 & 0x02) {
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if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
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(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
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!(v1 & 0x08))) {
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cs->dc.isac.mocr &= 0xf0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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cs->dc.isac.mocr |= 0x0a;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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if (cs->dc.isac.mon_txc &&
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(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
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schedule_event(cs, D_TX_MON0);
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goto AfterMOX0;
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}
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if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) {
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schedule_event(cs, D_TX_MON0);
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goto AfterMOX0;
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}
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cs->writeisac(cs, ISAC_MOX0,
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cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
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if (cs->debug & L1_DEB_MONITOR)
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debugl1(cs, "ISAC %02x -> MOX0", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp - 1]);
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}
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AfterMOX0:
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if (v1 & 0x20) {
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if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
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(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
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!(v1 & 0x80))) {
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cs->dc.isac.mocr &= 0x0f;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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cs->dc.isac.mocr |= 0xa0;
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cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
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if (cs->dc.isac.mon_txc &&
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(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
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schedule_event(cs, D_TX_MON1);
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goto AfterMOX1;
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}
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if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) {
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schedule_event(cs, D_TX_MON1);
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goto AfterMOX1;
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}
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cs->writeisac(cs, ISAC_MOX1,
|
|
cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
|
|
if (cs->debug & L1_DEB_MONITOR)
|
|
debugl1(cs, "ISAC %02x -> MOX1", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp - 1]);
|
|
}
|
|
AfterMOX1:;
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
ISAC_l1hw(struct PStack *st, int pr, void *arg)
|
|
{
|
|
struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
|
|
struct sk_buff *skb = arg;
|
|
u_long flags;
|
|
int val;
|
|
|
|
switch (pr) {
|
|
case (PH_DATA | REQUEST):
|
|
if (cs->debug & DEB_DLOG_HEX)
|
|
LogFrame(cs, skb->data, skb->len);
|
|
if (cs->debug & DEB_DLOG_VERBOSE)
|
|
dlogframe(cs, skb, 0);
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
if (cs->tx_skb) {
|
|
skb_queue_tail(&cs->sq, skb);
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
Logl2Frame(cs, skb, "PH_DATA Queued", 0);
|
|
#endif
|
|
} else {
|
|
cs->tx_skb = skb;
|
|
cs->tx_cnt = 0;
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
Logl2Frame(cs, skb, "PH_DATA", 0);
|
|
#endif
|
|
isac_fill_fifo(cs);
|
|
}
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
case (PH_PULL | INDICATION):
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
if (cs->tx_skb) {
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
|
|
skb_queue_tail(&cs->sq, skb);
|
|
} else {
|
|
if (cs->debug & DEB_DLOG_HEX)
|
|
LogFrame(cs, skb->data, skb->len);
|
|
if (cs->debug & DEB_DLOG_VERBOSE)
|
|
dlogframe(cs, skb, 0);
|
|
cs->tx_skb = skb;
|
|
cs->tx_cnt = 0;
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
|
|
#endif
|
|
isac_fill_fifo(cs);
|
|
}
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
case (PH_PULL | REQUEST):
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
debugl1(cs, "-> PH_REQUEST_PULL");
|
|
#endif
|
|
if (!cs->tx_skb) {
|
|
test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
|
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
|
|
} else
|
|
test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
|
break;
|
|
case (HW_RESET | REQUEST):
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
if ((cs->dc.isac.ph_state == ISAC_IND_EI) ||
|
|
(cs->dc.isac.ph_state == ISAC_IND_DR) ||
|
|
(cs->dc.isac.ph_state == ISAC_IND_RS))
|
|
ph_command(cs, ISAC_CMD_TIM);
|
|
else
|
|
ph_command(cs, ISAC_CMD_RS);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
case (HW_ENABLE | REQUEST):
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
ph_command(cs, ISAC_CMD_TIM);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
case (HW_INFO3 | REQUEST):
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
ph_command(cs, ISAC_CMD_AR8);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
case (HW_TESTLOOP | REQUEST):
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
val = 0;
|
|
if (1 & (long) arg)
|
|
val |= 0x0c;
|
|
if (2 & (long) arg)
|
|
val |= 0x3;
|
|
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
|
|
/* IOM 1 Mode */
|
|
if (!val) {
|
|
cs->writeisac(cs, ISAC_SPCR, 0xa);
|
|
cs->writeisac(cs, ISAC_ADF1, 0x2);
|
|
} else {
|
|
cs->writeisac(cs, ISAC_SPCR, val);
|
|
cs->writeisac(cs, ISAC_ADF1, 0xa);
|
|
}
|
|
} else {
|
|
/* IOM 2 Mode */
|
|
cs->writeisac(cs, ISAC_SPCR, val);
|
|
if (val)
|
|
cs->writeisac(cs, ISAC_ADF1, 0x8);
|
|
else
|
|
cs->writeisac(cs, ISAC_ADF1, 0x0);
|
|
}
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
case (HW_DEACTIVATE | RESPONSE):
|
|
skb_queue_purge(&cs->rq);
|
|
skb_queue_purge(&cs->sq);
|
|
if (cs->tx_skb) {
|
|
dev_kfree_skb_any(cs->tx_skb);
|
|
cs->tx_skb = NULL;
|
|
}
|
|
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
|
|
del_timer(&cs->dbusytimer);
|
|
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
|
|
schedule_event(cs, D_CLEARBUSY);
|
|
break;
|
|
default:
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "isac_l1hw unknown %04x", pr);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void
|
|
setstack_isac(struct PStack *st, struct IsdnCardState *cs)
|
|
{
|
|
st->l1.l1hw = ISAC_l1hw;
|
|
}
|
|
|
|
static void
|
|
DC_Close_isac(struct IsdnCardState *cs)
|
|
{
|
|
kfree(cs->dc.isac.mon_rx);
|
|
cs->dc.isac.mon_rx = NULL;
|
|
kfree(cs->dc.isac.mon_tx);
|
|
cs->dc.isac.mon_tx = NULL;
|
|
}
|
|
|
|
static void
|
|
dbusy_timer_handler(struct timer_list *t)
|
|
{
|
|
struct IsdnCardState *cs = from_timer(cs, t, dbusytimer);
|
|
struct PStack *stptr;
|
|
int rbch, star;
|
|
|
|
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
|
|
rbch = cs->readisac(cs, ISAC_RBCH);
|
|
star = cs->readisac(cs, ISAC_STAR);
|
|
if (cs->debug)
|
|
debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
|
|
rbch, star);
|
|
if (rbch & ISAC_RBCH_XAC) { /* D-Channel Busy */
|
|
test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
|
|
stptr = cs->stlist;
|
|
while (stptr != NULL) {
|
|
stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
|
|
stptr = stptr->next;
|
|
}
|
|
} else {
|
|
/* discard frame; reset transceiver */
|
|
test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
|
|
if (cs->tx_skb) {
|
|
dev_kfree_skb_any(cs->tx_skb);
|
|
cs->tx_cnt = 0;
|
|
cs->tx_skb = NULL;
|
|
} else {
|
|
printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
|
|
debugl1(cs, "D-Channel Busy no skb");
|
|
}
|
|
cs->writeisac(cs, ISAC_CMDR, 0x01); /* Transmitter reset */
|
|
cs->irq_func(cs->irq, cs);
|
|
}
|
|
}
|
|
}
|
|
|
|
void initisac(struct IsdnCardState *cs)
|
|
{
|
|
cs->setstack_d = setstack_isac;
|
|
cs->DC_Close = DC_Close_isac;
|
|
cs->dc.isac.mon_tx = NULL;
|
|
cs->dc.isac.mon_rx = NULL;
|
|
cs->writeisac(cs, ISAC_MASK, 0xff);
|
|
cs->dc.isac.mocr = 0xaa;
|
|
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
|
|
/* IOM 1 Mode */
|
|
cs->writeisac(cs, ISAC_ADF2, 0x0);
|
|
cs->writeisac(cs, ISAC_SPCR, 0xa);
|
|
cs->writeisac(cs, ISAC_ADF1, 0x2);
|
|
cs->writeisac(cs, ISAC_STCR, 0x70);
|
|
cs->writeisac(cs, ISAC_MODE, 0xc9);
|
|
} else {
|
|
/* IOM 2 Mode */
|
|
if (!cs->dc.isac.adf2)
|
|
cs->dc.isac.adf2 = 0x80;
|
|
cs->writeisac(cs, ISAC_ADF2, cs->dc.isac.adf2);
|
|
cs->writeisac(cs, ISAC_SQXR, 0x2f);
|
|
cs->writeisac(cs, ISAC_SPCR, 0x00);
|
|
cs->writeisac(cs, ISAC_STCR, 0x70);
|
|
cs->writeisac(cs, ISAC_MODE, 0xc9);
|
|
cs->writeisac(cs, ISAC_TIMR, 0x00);
|
|
cs->writeisac(cs, ISAC_ADF1, 0x00);
|
|
}
|
|
ph_command(cs, ISAC_CMD_RS);
|
|
cs->writeisac(cs, ISAC_MASK, 0x0);
|
|
}
|
|
|
|
void clear_pending_isac_ints(struct IsdnCardState *cs)
|
|
{
|
|
int val, eval;
|
|
|
|
val = cs->readisac(cs, ISAC_STAR);
|
|
debugl1(cs, "ISAC STAR %x", val);
|
|
val = cs->readisac(cs, ISAC_MODE);
|
|
debugl1(cs, "ISAC MODE %x", val);
|
|
val = cs->readisac(cs, ISAC_ADF2);
|
|
debugl1(cs, "ISAC ADF2 %x", val);
|
|
val = cs->readisac(cs, ISAC_ISTA);
|
|
debugl1(cs, "ISAC ISTA %x", val);
|
|
if (val & 0x01) {
|
|
eval = cs->readisac(cs, ISAC_EXIR);
|
|
debugl1(cs, "ISAC EXIR %x", eval);
|
|
}
|
|
val = cs->readisac(cs, ISAC_CIR0);
|
|
debugl1(cs, "ISAC CIR0 %x", val);
|
|
cs->dc.isac.ph_state = (val >> 2) & 0xf;
|
|
schedule_event(cs, D_L1STATECHANGE);
|
|
/* Disable all IRQ */
|
|
cs->writeisac(cs, ISAC_MASK, 0xFF);
|
|
}
|
|
|
|
void setup_isac(struct IsdnCardState *cs)
|
|
{
|
|
INIT_WORK(&cs->tqueue, isac_bh);
|
|
timer_setup(&cs->dbusytimer, dbusy_timer_handler, 0);
|
|
}
|