123 lines
3.1 KiB
C
123 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __ADSP_DVFS_H__
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#define __ADSP_DVFS_H__
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#include <adsp_ipi.h>
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#include <adsp_clk.h>
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#define ADSP_ITCM_MONITOR (1)
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#define ADSP_DTCM_MONITOR (1)
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#define ADSP_CFG_MONITOR (0)
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#define ADSP_DVFS_PROFILE (1)
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#define ADSP_FREQ_METER_ID (43) //hf_fadsp_ck
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#define ADSP_DVFS_USE_PLL 1
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#define PLL_ENABLE (1)
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#define PLL_DISABLE (0)
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#define DVFS_STATUS_OK (0)
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#define DVFS_STATUS_BUSY (-1)
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#define DVFS_REQUEST_SAME_CLOCK (-2)
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#define DVFS_STATUS_ERR (-3)
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#define DVFS_STATUS_TIMEOUT (-4)
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#define DVFS_CLK_ERROR (-5)
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#define DVFS_STATUS_CMD_FIX (-6)
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#define DVFS_STATUS_CMD_LIMITED (-7)
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#define DVFS_STATUS_CMD_DISABLE (-8)
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enum adsp_cur_status_enum {
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ADSP_STATUS_RESET = 0x00,
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ADSP_STATUS_SUSPEND = 0x01,
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ADSP_STATUS_SLEEP = 0x10,
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ADSP_STATUS_ACTIVE = 0x11,
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};
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enum adsp_state_enum {
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IN_DEBUG_IDLE = 1,
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ENTERING_SLEEP = 2,
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IN_SLEEP = 4,
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ENTERING_ACTIVE = 8,
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IN_ACTIVE = 16,
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};
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enum {
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CLK_SYS_EN_BIT = 0,
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CLK_HIGH_EN_BIT = 1,
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CLK_HIGH_CG_BIT = 2,
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CLK_SYS_IRQ_EN_BIT = 16,
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CLK_HIGH_IRQ_EN_BIT = 17,
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};
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/*#ifdef CONFIG_PINCTRL_MT6797*/
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enum clk_opp_enum {
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CLK_OPP0 = 125,
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CLK_OPP1 = 330,
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CLK_OPP2 = 416,
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CLK_INVALID_OPP,
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};
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enum clk_div_enum {
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CLK_DIV_1 = 0,
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CLK_DIV_2 = 1,
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CLK_DIV_4 = 2,
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CLK_DIV_8 = 3,
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CLK_DIV_UNKNOWN,
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};
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enum voltage_enum {
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SPM_VOLTAGE_800_D = 0,
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SPM_VOLTAGE_800,
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SPM_VOLTAGE_900,
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SPM_VOLTAGE_1000,
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SPM_VOLTAGE_TYPE_NUM,
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};
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struct mt_adsp_pll_t {
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/* main clock for mfg setting */
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struct clk *clk_mux;
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/* substitution clock for adsp transient parent setting */
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struct clk *clk_pll0;
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struct clk *clk_pll1;
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struct clk *clk_pll2;
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struct clk *clk_pll3;
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struct clk *clk_pll4;
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struct clk *clk_pll5;
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struct clk *clk_pll6;
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struct clk *clk_pll7;
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};
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extern int adsp_pll_ctrl_set(unsigned int pll_ctrl_flag, unsigned int pll_sel);
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extern int adsp_set_pmic_vcore(unsigned int cur_freq);
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extern unsigned int adsp_get_dvfs_opp(void);
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extern uint32_t adsp_get_freq(void);
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extern int adsp_request_freq(void);
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extern void adsp_pll_mux_set(unsigned int pll_ctrl_flag);
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extern void wait_adsp_dvfs_init_done(void);
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extern int __init adsp_dvfs_init(void);
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extern void __exit adsp_dvfs_exit(void);
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/* adsp dvfs variable*/
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extern struct mutex adsp_feature_mutex;
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extern struct mutex adsp_suspend_mutex;
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extern struct completion adsp_suspend_cp;
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extern struct completion adsp_resume_cp;
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extern int adsp_is_suspend;
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/* adsp new implement */
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void adsp_A_send_spm_request(uint32_t enable);
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extern void adsp_reset(void);
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void adsp_sw_reset(enum adsp_core_id core_id);
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extern void adsp_release_runstall(enum adsp_core_id, uint32_t release);
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extern int adsp_suspend_init(void);
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void adsp_start_suspend_timer(void);
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void adsp_stop_suspend_timer(void);
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int adsp_resume(void);
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void adsp_suspend(enum adsp_core_id core_id);
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/***************************/
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#endif /* __ADSP_DVFS_H__ */
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