57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_LPAE_H__
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#define __MTK_LPAE_H__
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#ifdef CONFIG_MTK_LM_MODE
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#include <mt-plat/mtk_io.h>
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#define INTERAL_MAPPING_OFFSET (0x40000000)
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#define INTERAL_MAPPING_LIMIT (INTERAL_MAPPING_OFFSET + 0x80000000)
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#define MT_OVERFLOW_ADDR_START 0x100000000ULL
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unsigned int __attribute__((weak)) enable_4G(void)
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{
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return 0;
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}
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/* For HW modules which support 33-bit address setting */
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#define CROSS_OVERFLOW_ADDR_TRANSFER(phy_addr, size, ret) \
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do { \
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ret = 0; \
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if (enable_4G()) {\
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if (((phys_addr_t)phy_addr < MT_OVERFLOW_ADDR_START)\
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&& (((phys_addr_t)phy_addr + size) >= \
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MT_OVERFLOW_ADDR_START)) \
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ret = MT_OVERFLOW_ADDR_START - phy_addr; \
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} \
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} while (0) \
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/* For SPM and MD32 only in ROME */
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#define MAPPING_DRAM_ACCESS_ADDR(phy_addr) \
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do { \
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if (enable_4G()) {\
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if (phy_addr >= INTERAL_MAPPING_OFFSET \
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&& phy_addr < INTERAL_MAPPING_LIMIT) \
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phy_addr += INTERAL_MAPPING_OFFSET; \
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} \
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} while (0)\
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#else /* !CONFIG_ARM_LPAE */
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#define CROSS_OVERFLOW_ADDR_TRANSFER(phy_addr, size, ret)
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#define MAPPING_DRAM_ACCESS_ADDR(phy_addr)
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#define MT_OVERFLOW_ADDR_START 0
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static inline unsigned int enable_4G(void)
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{
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return 0;
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}
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#endif
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#endif /*!__MTK_LPAE_H__ */
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