189 lines
4.1 KiB
C
189 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 MediaTek Inc.
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*/
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#include <linux/string.h>
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#include "mmdvfs_plat.h"
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#include "mtk_qos_sram.h"
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#include "smi_pmqos.h"
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#if IS_ENABLED(CONFIG_MACH_MT6877)
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#if defined(USE_MEDIATEK_EMI)
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#include <memory/mediatek/dramc.h>
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#endif
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#include <dt-bindings/memory/mt6877-larb-port.h>
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#else
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#include <dt-bindings/memory/mt6853-larb-port.h>
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#endif
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#undef pr_fmt
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#define pr_fmt(fmt) "[mmdvfs][plat]" fmt
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#define LARB_MDP_ID 2
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#define LARB_VENC_ID 7
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#define LARB_IMG_ID 9
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#define LARB_IMG2_ID 11
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#define LARB_CAM_ID 13
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#define LARB_CAM2_ID 14
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#define LARB_CAM3_ID 16
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#define LARB_CAM4_ID 17
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static const u32 mdp_comm_port_shift = (0 * SMI_COMM_MASTER_NUM + 4);
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static const u32 venc_comm_port_shift = (0 * SMI_COMM_MASTER_NUM + 3);
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static const u32 img_comm_port_shift = (0 * SMI_COMM_MASTER_NUM + 5);
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static const u32 cam_comm_port_shift = (0 * SMI_COMM_MASTER_NUM + 6);
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static const u32 cam_comm_port2_shift = (0 * SMI_COMM_MASTER_NUM + 7);
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#ifdef QOS_BOUND_DETECT
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void mmdvfs_update_qos_sram(struct mm_larb_request larb_req[], u32 larb_update)
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{
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u32 bw;
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if (larb_update & (1 << mdp_comm_port_shift)) {
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bw = larb_req[LARB_MDP_ID].total_bw_data;
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qos_sram_write(MM_SMI_MDP, bw);
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}
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if (larb_update & (1 << venc_comm_port_shift)) {
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bw = larb_req[LARB_VENC_ID].total_bw_data;
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//bw += larb_req[LARB_VENC2_ID].total_bw_data;
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qos_sram_write(MM_SMI_VENC, bw);
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}
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if (larb_update & (1 << img_comm_port_shift)) {
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bw = larb_req[LARB_IMG_ID].total_bw_data;
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qos_sram_write(MM_SMI_IMG, bw);
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}
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if (larb_update & ((1 << cam_comm_port_shift)
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| (1 << cam_comm_port2_shift))) {
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bw = larb_req[LARB_CAM_ID].total_bw_data;
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bw += larb_req[LARB_CAM2_ID].total_bw_data;
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bw += larb_req[LARB_CAM3_ID].total_bw_data;
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bw += larb_req[LARB_CAM4_ID].total_bw_data;
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qos_sram_write(MM_SMI_CAM, bw);
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}
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}
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#endif
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static u32 log_common_port_ids;
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static u32 log_larb_ids;
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bool mmdvfs_log_larb_mmp(s32 common_port_id, s32 larb_id)
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{
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if (common_port_id >= 0)
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return (1 << common_port_id) & log_common_port_ids;
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if (larb_id >= 0)
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return (1 << larb_id) & log_larb_ids;
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return false;
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}
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/* Return port number of CCU on SMI common */
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inline u32 mmdvfs_get_ccu_smi_common_port(u32 master_id)
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{
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if (master_id == get_virtual_port(VIRTUAL_CCU_COMMON))
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return 7;
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else
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return 6;
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}
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s32 get_ccu_hrt_bw(struct mm_larb_request larb_req[])
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{
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struct mm_qos_request *enum_req = NULL;
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s32 bw = larb_req[MTK_IOMMU_TO_LARB(get_virtual_port(
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VIRTUAL_CCU_COMMON))].total_hrt_data;
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bw += larb_req[MTK_IOMMU_TO_LARB(get_virtual_port(
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VIRTUAL_CCU_COMMON2))].total_hrt_data;
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list_for_each_entry(enum_req,
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&larb_req[LARB_CAM_ID].larb_list, larb_node) {
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if (enum_req->master_id == M4U_PORT_L13_CAM_CCUI
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|| enum_req->master_id == M4U_PORT_L13_CAM_CCUO)
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bw += enum_req->hrt_value;
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}
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list_for_each_entry(enum_req,
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&larb_req[LARB_CAM2_ID].larb_list, larb_node) {
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if (enum_req->master_id == M4U_PORT_L14_CAM_CCUI
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|| enum_req->master_id == M4U_PORT_L14_CAM_CCUO)
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bw += enum_req->hrt_value;
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}
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return bw;
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}
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s32 get_md_hrt_bw(void)
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{
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#if IS_ENABLED(CONFIG_MACH_MT6853)
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return 3344;
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#elif IS_ENABLED(CONFIG_MACH_MT6877)
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return (3427*100/65+1700);
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#elif IS_ENABLED(CONFIG_MACH_MT6781)
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return 1843;
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#else
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return 3888;
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#endif
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}
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s32 dram_write_weight(s32 val)
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{
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return val;
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}
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s32 emi_occ_ratio(void)
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{
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#if IS_ENABLED(CONFIG_MACH_MT6877)
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#if defined(USE_MEDIATEK_EMI)
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if (mtk_dramc_get_ddr_type() == TYPE_LPDDR5)
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return 680;
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#endif
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return 740;
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#else
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return 500;
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#endif
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}
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s32 emi_occ_ui_only(void)
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{
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#if IS_ENABLED(CONFIG_MACH_MT6877)
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#if defined(USE_MEDIATEK_EMI)
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if (mtk_dramc_get_ddr_type() == TYPE_LPDDR5)
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return 680;
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#endif
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return 745;
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#else
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return 500;
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#endif
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}
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s32 cam_occ_ratio(void)
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{
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#if IS_ENABLED(CONFIG_MACH_MT6877)
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#if defined(USE_MEDIATEK_EMI)
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if (mtk_dramc_get_ddr_type() == TYPE_LPDDR5)
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return 860;
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#endif
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return 880;
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#else
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return 1000;
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#endif
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}
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s32 disp_occ_ratio(void)
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{
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#if IS_ENABLED(CONFIG_MACH_MT6877)
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#if defined(USE_MEDIATEK_EMI)
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if (mtk_dramc_get_ddr_type() == TYPE_LPDDR5)
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return 880;
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#endif
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return 900;
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#else
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return 1000;
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#endif
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}
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