319 lines
7.8 KiB
C
319 lines
7.8 KiB
C
/*
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* Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/delay.h>
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#include "mt76x2u.h"
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#include "mt76x2_eeprom.h"
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static void mt76x2u_init_dma(struct mt76x2_dev *dev)
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{
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u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
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val |= MT_USB_DMA_CFG_RX_DROP_OR_PAD |
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MT_USB_DMA_CFG_RX_BULK_EN |
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MT_USB_DMA_CFG_TX_BULK_EN;
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/* disable AGGR_BULK_RX in order to receive one
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* frame in each rx urb and avoid copies
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*/
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val &= ~MT_USB_DMA_CFG_RX_BULK_AGG_EN;
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mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);
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}
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static void mt76x2u_power_on_rf_patch(struct mt76x2_dev *dev)
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{
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16));
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udelay(1);
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mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff);
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30);
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mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f);
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udelay(1);
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17));
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usleep_range(150, 200);
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mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16));
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usleep_range(50, 100);
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20));
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}
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static void mt76x2u_power_on_rf(struct mt76x2_dev *dev, int unit)
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{
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int shift = unit ? 8 : 0;
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u32 val = (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift;
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/* Enable RF BG */
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift);
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usleep_range(10, 20);
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/* Enable RFDIG LDO/AFE/ABB/ADDA */
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val);
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usleep_range(10, 20);
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/* Switch RFDIG power to internal LDO */
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mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(2) << shift);
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usleep_range(10, 20);
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mt76x2u_power_on_rf_patch(dev);
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mt76_set(dev, 0x530, 0xf);
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}
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static void mt76x2u_power_on(struct mt76x2_dev *dev)
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{
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u32 val;
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/* Turn on WL MTCMOS */
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x148),
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MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
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val = MT_WLAN_MTC_CTRL_STATE_UP |
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MT_WLAN_MTC_CTRL_PWR_ACK |
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MT_WLAN_MTC_CTRL_PWR_ACK_S;
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mt76_poll(dev, MT_VEND_ADDR(CFG, 0x148), val, val, 1000);
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mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0x7f << 16);
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usleep_range(10, 20);
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mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24);
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usleep_range(10, 20);
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24);
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mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xfff);
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/* Turn on AD/DA power down */
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mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1204), BIT(3));
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/* WLAN function enable */
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mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0));
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/* Release BBP software reset */
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mt76_clear(dev, MT_VEND_ADDR(CFG, 0x64), BIT(18));
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mt76x2u_power_on_rf(dev, 0);
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mt76x2u_power_on_rf(dev, 1);
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}
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static int mt76x2u_init_eeprom(struct mt76x2_dev *dev)
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{
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u32 val, i;
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dev->mt76.eeprom.data = devm_kzalloc(dev->mt76.dev,
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MT7612U_EEPROM_SIZE,
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GFP_KERNEL);
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dev->mt76.eeprom.size = MT7612U_EEPROM_SIZE;
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if (!dev->mt76.eeprom.data)
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return -ENOMEM;
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for (i = 0; i + 4 <= MT7612U_EEPROM_SIZE; i += 4) {
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val = mt76_rr(dev, MT_VEND_ADDR(EEPROM, i));
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put_unaligned_le32(val, dev->mt76.eeprom.data + i);
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}
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mt76x2_eeprom_parse_hw_cap(dev);
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return 0;
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}
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struct mt76x2_dev *mt76x2u_alloc_device(struct device *pdev)
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{
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static const struct mt76_driver_ops drv_ops = {
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.tx_prepare_skb = mt76x2u_tx_prepare_skb,
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.tx_complete_skb = mt76x2u_tx_complete_skb,
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.tx_status_data = mt76x2u_tx_status_data,
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.rx_skb = mt76x2_queue_rx_skb,
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};
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struct mt76x2_dev *dev;
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struct mt76_dev *mdev;
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mdev = mt76_alloc_device(sizeof(*dev), &mt76x2u_ops);
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if (!mdev)
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return NULL;
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dev = container_of(mdev, struct mt76x2_dev, mt76);
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mdev->dev = pdev;
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mdev->drv = &drv_ops;
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mutex_init(&dev->mutex);
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return dev;
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}
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static void mt76x2u_init_beacon_offsets(struct mt76x2_dev *dev)
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{
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mt76_wr(dev, MT_BCN_OFFSET(0), 0x18100800);
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mt76_wr(dev, MT_BCN_OFFSET(1), 0x38302820);
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mt76_wr(dev, MT_BCN_OFFSET(2), 0x58504840);
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mt76_wr(dev, MT_BCN_OFFSET(3), 0x78706860);
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}
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int mt76x2u_init_hardware(struct mt76x2_dev *dev)
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{
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static const u16 beacon_offsets[] = {
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/* 512 byte per beacon */
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0xc000, 0xc200, 0xc400, 0xc600,
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0xc800, 0xca00, 0xcc00, 0xce00,
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0xd000, 0xd200, 0xd400, 0xd600,
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0xd800, 0xda00, 0xdc00, 0xde00
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};
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const struct mt76_wcid_addr addr = {
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.macaddr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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.ba_mask = 0,
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};
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int i, err;
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dev->beacon_offsets = beacon_offsets;
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mt76x2_reset_wlan(dev, true);
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mt76x2u_power_on(dev);
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if (!mt76x2_wait_for_mac(dev))
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return -ETIMEDOUT;
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err = mt76x2u_mcu_fw_init(dev);
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if (err < 0)
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return err;
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if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100))
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return -EIO;
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/* wait for asic ready after fw load. */
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if (!mt76x2_wait_for_mac(dev))
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return -ETIMEDOUT;
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mt76_wr(dev, MT_HEADER_TRANS_CTRL_REG, 0);
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mt76_wr(dev, MT_TSO_CTRL, 0);
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mt76x2u_init_dma(dev);
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err = mt76x2u_mcu_init(dev);
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if (err < 0)
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return err;
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err = mt76x2u_mac_reset(dev);
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if (err < 0)
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return err;
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mt76x2u_mac_setaddr(dev, dev->mt76.eeprom.data + MT_EE_MAC_ADDR);
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dev->rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
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mt76x2u_init_beacon_offsets(dev);
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if (!mt76x2_wait_for_bbp(dev))
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return -ETIMEDOUT;
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/* reset wcid table */
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for (i = 0; i < 254; i++)
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mt76_wr_copy(dev, MT_WCID_ADDR(i), &addr,
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sizeof(struct mt76_wcid_addr));
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/* reset shared key table and pairwise key table */
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for (i = 0; i < 4; i++)
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mt76_wr(dev, MT_SKEY_MODE_BASE_0 + 4 * i, 0);
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for (i = 0; i < 256; i++)
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mt76_wr(dev, MT_WCID_ATTR(i), 1);
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mt76_clear(dev, MT_BEACON_TIME_CFG,
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MT_BEACON_TIME_CFG_TIMER_EN |
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MT_BEACON_TIME_CFG_SYNC_MODE |
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MT_BEACON_TIME_CFG_TBTT_EN |
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MT_BEACON_TIME_CFG_BEACON_TX);
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mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
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mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x583f);
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err = mt76x2u_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0);
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if (err < 0)
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return err;
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mt76x2u_phy_set_rxpath(dev);
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mt76x2u_phy_set_txdac(dev);
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return mt76x2u_mac_stop(dev);
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}
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int mt76x2u_register_device(struct mt76x2_dev *dev)
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{
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struct ieee80211_hw *hw = mt76_hw(dev);
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struct wiphy *wiphy = hw->wiphy;
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int err;
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INIT_DELAYED_WORK(&dev->cal_work, mt76x2u_phy_calibrate);
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mt76x2_init_device(dev);
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err = mt76x2u_init_eeprom(dev);
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if (err < 0)
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return err;
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err = mt76u_mcu_init_rx(&dev->mt76);
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if (err < 0)
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return err;
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err = mt76u_alloc_queues(&dev->mt76);
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if (err < 0)
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goto fail;
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err = mt76x2u_init_hardware(dev);
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if (err < 0)
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goto fail;
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wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
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err = mt76_register_device(&dev->mt76, true, mt76x2_rates,
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ARRAY_SIZE(mt76x2_rates));
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if (err)
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goto fail;
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/* check hw sg support in order to enable AMSDU */
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if (mt76u_check_sg(&dev->mt76))
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hw->max_tx_fragments = MT_SG_MAX_SIZE;
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else
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hw->max_tx_fragments = 1;
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set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
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mt76x2_init_debugfs(dev);
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mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband);
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mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband);
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return 0;
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fail:
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mt76x2u_cleanup(dev);
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return err;
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}
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void mt76x2u_stop_hw(struct mt76x2_dev *dev)
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{
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mt76u_stop_stat_wk(&dev->mt76);
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cancel_delayed_work_sync(&dev->cal_work);
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mt76x2u_mac_stop(dev);
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}
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void mt76x2u_cleanup(struct mt76x2_dev *dev)
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{
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mt76x2u_mcu_set_radio_state(dev, false);
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mt76x2u_stop_hw(dev);
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mt76u_queues_deinit(&dev->mt76);
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mt76x2u_mcu_deinit(dev);
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}
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