169 lines
4.6 KiB
C
169 lines
4.6 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL92C_DEF_H__
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#define __RTL92C_DEF_H__
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#define PHY_RSSI_SLID_WIN_MAX 100
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#define PHY_LINKQUALITY_SLID_WIN_MAX 20
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#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
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#define RX_SMOOTH_FACTOR 20
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#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
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#define HAL_PRIME_CHNL_OFFSET_LOWER 1
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#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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#define RX_MPDU_QUEUE 0
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#define RX_CMD_QUEUE 1
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#define C2H_RX_CMD_HDR_LEN 8
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#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
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#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
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#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
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#define GET_C2H_CMD_CONTINUE(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
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#define GET_C2H_CMD_CONTENT(__prxhdr) \
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((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
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#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
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#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
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#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
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#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
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#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
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#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
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#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
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#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
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#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
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#define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc) \
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SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32)
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#define CHIP_VER_B BIT(4)
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
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#define CHIP_BONDING_92C_1T2R 0x1
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#define RF_TYPE_1T2R BIT(1)
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#define CHIP_92C_BITMASK BIT(0)
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#define CHIP_UNKNOWN BIT(7)
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#define CHIP_92C_1T2R 0x03
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#define CHIP_92C 0x01
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#define CHIP_88C 0x00
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enum version_8192c {
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VERSION_A_CHIP_92C = 0x01,
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VERSION_A_CHIP_88C = 0x00,
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VERSION_B_CHIP_92C = 0x11,
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VERSION_B_CHIP_88C = 0x10,
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VERSION_TEST_CHIP_88C = 0x00,
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VERSION_TEST_CHIP_92C = 0x01,
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VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
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VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
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VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
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VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
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VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
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VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
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VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
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VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
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VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
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VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
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VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
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VERSION_UNKNOWN = 0x88,
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};
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enum rtl819x_loopback_e {
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RTL819X_NO_LOOPBACK = 0,
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RTL819X_MAC_LOOPBACK = 1,
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RTL819X_DMA_LOOPBACK = 2,
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RTL819X_CCK_LOOPBACK = 3,
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};
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enum rf_optype {
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RF_OP_BY_SW_3WIRE = 0,
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RF_OP_BY_FW,
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RF_OP_MAX
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};
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enum rf_power_state {
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RF_ON,
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RF_OFF,
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RF_SLEEP,
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RF_SHUT_DOWN,
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};
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enum power_save_mode {
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POWER_SAVE_MODE_ACTIVE,
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POWER_SAVE_MODE_SAVE,
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};
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enum power_polocy_config {
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POWERCFG_MAX_POWER_SAVINGS,
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POWERCFG_GLOBAL_POWER_SAVINGS,
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POWERCFG_LOCAL_POWER_SAVINGS,
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POWERCFG_LENOVO,
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};
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enum interface_select_pci {
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INTF_SEL1_MINICARD = 0,
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INTF_SEL0_PCIE = 1,
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INTF_SEL2_RSV = 2,
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INTF_SEL3_RSV = 3,
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};
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enum rtl_desc_qsel {
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QSLT_BK = 0x2,
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QSLT_BE = 0x0,
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QSLT_VI = 0x5,
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QSLT_VO = 0x7,
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QSLT_BEACON = 0x10,
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QSLT_HIGH = 0x11,
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QSLT_MGNT = 0x12,
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QSLT_CMD = 0x13,
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};
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struct phy_sts_cck_8192s_t {
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u8 adc_pwdb_X[4];
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u8 sq_rpt;
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u8 cck_agc_rpt;
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};
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struct h2c_cmd_8192c {
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u8 element_id;
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u32 cmd_len;
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u8 *p_cmdbuffer;
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};
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#endif
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