183 lines
4.8 KiB
C
183 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* OWL SoC's Pinctrl definitions
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*
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* Copyright (c) 2014 Actions Semi Inc.
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* Author: David Liu <liuwei@actions-semi.com>
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*
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* Copyright (c) 2018 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#ifndef __PINCTRL_OWL_H__
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#define __PINCTRL_OWL_H__
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#define OWL_PINCONF_SLEW_SLOW 0
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#define OWL_PINCONF_SLEW_FAST 1
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enum owl_pinconf_pull {
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OWL_PINCONF_PULL_HIZ,
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OWL_PINCONF_PULL_DOWN,
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OWL_PINCONF_PULL_UP,
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OWL_PINCONF_PULL_HOLD,
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};
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enum owl_pinconf_drv {
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OWL_PINCONF_DRV_2MA,
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OWL_PINCONF_DRV_4MA,
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OWL_PINCONF_DRV_8MA,
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OWL_PINCONF_DRV_12MA,
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};
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/* GPIO CTRL Bit Definition */
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#define OWL_GPIO_CTLR_PENDING 0
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#define OWL_GPIO_CTLR_ENABLE 1
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#define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2
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/* GPIO TYPE Bit Definition */
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#define OWL_GPIO_INT_LEVEL_HIGH 0
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#define OWL_GPIO_INT_LEVEL_LOW 1
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#define OWL_GPIO_INT_EDGE_RISING 2
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#define OWL_GPIO_INT_EDGE_FALLING 3
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#define OWL_GPIO_INT_MASK 3
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/**
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* struct owl_pullctl - Actions pad pull control register
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* @reg: offset to the pull control register
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* @shift: shift value of the register
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* @width: width of the register
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*/
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struct owl_pullctl {
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int reg;
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unsigned int shift;
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unsigned int width;
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};
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/**
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* struct owl_st - Actions pad schmitt trigger enable register
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* @reg: offset to the schmitt trigger enable register
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* @shift: shift value of the register
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* @width: width of the register
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*/
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struct owl_st {
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int reg;
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unsigned int shift;
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unsigned int width;
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};
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/**
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* struct owl_pingroup - Actions pingroup definition
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* @name: name of the pin group
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* @pads: list of pins assigned to this pingroup
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* @npads: size of @pads array
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* @funcs: list of pinmux functions for this pingroup
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* @nfuncs: size of @funcs array
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* @mfpctl_reg: multiplexing control register offset
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* @mfpctl_shift: multiplexing control register bit mask
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* @mfpctl_width: multiplexing control register width
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* @drv_reg: drive control register offset
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* @drv_shift: drive control register bit mask
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* @drv_width: driver control register width
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* @sr_reg: slew rate control register offset
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* @sr_shift: slew rate control register bit mask
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* @sr_width: slew rate control register width
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*/
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struct owl_pingroup {
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const char *name;
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unsigned int *pads;
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unsigned int npads;
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unsigned int *funcs;
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unsigned int nfuncs;
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int mfpctl_reg;
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unsigned int mfpctl_shift;
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unsigned int mfpctl_width;
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int drv_reg;
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unsigned int drv_shift;
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unsigned int drv_width;
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int sr_reg;
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unsigned int sr_shift;
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unsigned int sr_width;
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};
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/**
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* struct owl_padinfo - Actions pinctrl pad info
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* @pad: pad name of the SoC
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* @pullctl: pull control register info
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* @st: schmitt trigger register info
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*/
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struct owl_padinfo {
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int pad;
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struct owl_pullctl *pullctl;
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struct owl_st *st;
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};
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/**
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* struct owl_pinmux_func - Actions pinctrl mux functions
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* @name: name of the pinmux function.
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* @groups: array of pin groups that may select this function.
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* @ngroups: number of entries in @groups.
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*/
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struct owl_pinmux_func {
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const char *name;
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const char * const *groups;
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unsigned int ngroups;
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};
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/**
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* struct owl_gpio_port - Actions GPIO port info
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* @offset: offset of the GPIO port.
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* @pins: number of pins belongs to the GPIO port.
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* @outen: offset of the output enable register.
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* @inen: offset of the input enable register.
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* @dat: offset of the data register.
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* @intc_ctl: offset of the interrupt control register.
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* @intc_pd: offset of the interrupt pending register.
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* @intc_msk: offset of the interrupt mask register.
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* @intc_type: offset of the interrupt type register.
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*/
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struct owl_gpio_port {
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unsigned int offset;
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unsigned int pins;
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unsigned int outen;
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unsigned int inen;
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unsigned int dat;
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unsigned int intc_ctl;
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unsigned int intc_pd;
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unsigned int intc_msk;
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unsigned int intc_type;
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};
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/**
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* struct owl_pinctrl_soc_data - Actions pin controller driver configuration
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* @pins: array describing all pins of the pin controller.
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* @npins: number of entries in @pins.
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* @functions: array describing all mux functions of this SoC.
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* @nfunction: number of entries in @functions.
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* @groups: array describing all pin groups of this SoC.
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* @ngroups: number of entries in @groups.
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* @padinfo: array describing the pad info of this SoC.
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* @ngpios: number of pingroups the driver should expose as GPIOs.
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* @ports: array describing all GPIO ports of this SoC.
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* @nports: number of GPIO ports in this SoC.
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*/
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struct owl_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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unsigned int npins;
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const struct owl_pinmux_func *functions;
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unsigned int nfunctions;
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const struct owl_pingroup *groups;
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unsigned int ngroups;
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const struct owl_padinfo *padinfo;
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unsigned int ngpios;
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const struct owl_gpio_port *ports;
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unsigned int nports;
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};
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int owl_pinctrl_probe(struct platform_device *pdev,
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struct owl_pinctrl_soc_data *soc_data);
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#endif /* __PINCTRL_OWL_H__ */
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