242 lines
6.4 KiB
C
242 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_PE4_H
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#define __MTK_PE4_H
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#include "mtk_charger_algorithm_class.h"
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#define V_CHARGER_MIN 4600000 /* 4.6 V */
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/* pe4 */
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#define PE40_MAX_VBUS 11000
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#define PE40_MAX_IBUS 3000
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#define HIGH_TEMP_TO_LEAVE_PE40 46
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#define HIGH_TEMP_TO_ENTER_PE40 39
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#define LOW_TEMP_TO_LEAVE_PE40 10
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#define LOW_TEMP_TO_ENTER_PE40 10
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#define IBUS_ERR 14
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/*dual charger */
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#define PE4_SLAVE_MIVR_DIFF 100000
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#define PE4_ERROR_LEVEL 1
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#define PE4_INFO_LEVEL 2
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#define PE4_DEBUG_LEVEL 3
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extern int pe4_get_debug_level(void);
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#define pe4_err(fmt, args...) \
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do { \
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if (pe4_get_debug_level() >= PE4_ERROR_LEVEL) { \
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pr_notice(fmt, ##args); \
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} \
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} while (0)
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#define pe4_info(fmt, args...) \
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do { \
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if (pe4_get_debug_level() >= PE4_INFO_LEVEL) { \
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pr_notice(fmt, ##args); \
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} \
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} while (0)
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#define pe4_dbg(fmt, args...) \
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do { \
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if (pe4_get_debug_level() >= PE4_DEBUG_LEVEL) { \
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pr_notice(fmt, ##args); \
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} \
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} while (0)
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#define PD_CAP_MAX_NR 10
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struct pe4_pps_status {
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int output_mv; /* 0xffff means no support */
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int output_ma; /* 0xff means no support */
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uint8_t real_time_flags;
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};
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enum adapter_pe4_return_value {
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MTK_ADAPTER_PE4_OK = 0,
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MTK_ADAPTER_PE4_NOT_SUPPORT,
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MTK_ADAPTER_PE4_TIMEOUT,
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MTK_ADAPTER_PE4_REJECT,
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MTK_ADAPTER_PE4_ERROR,
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MTK_ADAPTER_PE4_ADJUST,
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};
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struct pe4_power_cap {
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uint8_t selected_cap_idx;
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uint8_t nr;
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uint8_t pdp;
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uint8_t pwr_limit[PD_CAP_MAX_NR];
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int max_mv[PD_CAP_MAX_NR];
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int min_mv[PD_CAP_MAX_NR];
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int ma[PD_CAP_MAX_NR];
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int maxwatt[PD_CAP_MAX_NR];
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int minwatt[PD_CAP_MAX_NR];
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uint8_t type[PD_CAP_MAX_NR];
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int info[PD_CAP_MAX_NR];
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};
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enum pe4_state_enum {
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PE4_HW_UNINIT = 0,
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PE4_HW_FAIL,
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PE4_HW_READY,
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PE4_TA_NOT_SUPPORT,
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PE4_INIT,
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PE4_RUN,
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PE4_TUNING,
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PE4_POSTCC,
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};
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struct pe4_adapter_status {
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int temperature;
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bool ocp;
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bool otp;
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bool ovp;
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};
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struct mtk_pe40 {
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struct platform_device *pdev;
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struct chg_alg_device *alg;
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struct mutex access_lock;
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struct mutex data_lock;
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struct wakeup_source *suspend_lock;
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bool can_query;
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int state;
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struct pe4_power_cap cap;
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struct power_supply *bat_psy;
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int avbus;
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int vbus;
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int ibus;
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int watt;
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int r_sw;
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int r_cable;
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int r_cable_1;
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int r_cable_2;
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int pmic_vbus;
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int TA_vbus;
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int vbus_cali;
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int max_charger_ibus;
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int max_vbus;
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int max_ibus;
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/* limitation by cable*/
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int pe4_input_current_limit;
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int pe4_input_current_limit_setting;
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/* module parameters */
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int cv;
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int input_current_limit1;
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int input_current_limit2;
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int charging_current_limit1;
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int charging_current_limit2;
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/* Current setting value */
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int charger_current1;
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int charger_current2;
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int input_current1;
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int input_current2;
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int polling_interval;
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/* dtsi */
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/* single charger */
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int sc_charger_current;
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int sc_input_current;
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/* dual charger in series */
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int dcs_input_current;
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int dcs_chg1_charger_current;
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int dcs_chg2_charger_current;
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int min_charger_voltage;
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int pe40_max_vbus;
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int pe40_max_ibus;
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int pe40_stop_battery_soc;
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int high_temp_to_leave_pe40;
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int high_temp_to_enter_pe40;
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int low_temp_to_leave_pe40;
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int low_temp_to_enter_pe40;
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int ibus_err;
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int dual_polling_ieoc;
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int slave_mivr_diff;
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/* pe4.0 cable impedance threshold (mohm) */
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u32 pe40_r_cable_1a_lower;
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u32 pe40_r_cable_2a_lower;
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u32 pe40_r_cable_3a_lower;
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};
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extern int pe4_hal_init_hardware(struct chg_alg_device *alg);
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extern int pe4_hal_enable_vbus_ovp(struct chg_alg_device *alg, bool enable);
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extern int pe4_hal_get_uisoc(struct chg_alg_device *alg);
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extern int pe4_hal_is_pd_adapter_ready(struct chg_alg_device *alg);
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extern int pe4_hal_get_battery_temperature(struct chg_alg_device *alg);
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extern int pe4_hal_set_input_current(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 ua);
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extern int pe4_hal_set_charging_current(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 ua);
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extern int pe4_hal_1st_set_adapter_cap(struct chg_alg_device *alg,
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int mV, int mA);
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extern int pe4_hal_set_adapter_cap(struct chg_alg_device *alg,
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int mV, int mA);
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extern int pe4_hal_set_adapter_cap_end(struct chg_alg_device *alg,
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int mV, int mA);
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extern int pe40_hal_get_adapter_status(struct chg_alg_device *alg,
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struct pe4_adapter_status *pe4_sta);
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extern int pe4_hal_get_adapter_cap(struct chg_alg_device *alg,
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struct pe4_power_cap *cap);
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extern int pe4_hal_get_input_current(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 *ua);
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extern int pe4_hal_enable_powerpath(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool enable);
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extern int pe4_hal_get_charger_cnt(struct chg_alg_device *alg);
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extern bool pe4_hal_is_chip_enable(struct chg_alg_device *alg,
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enum chg_idx chgidx);
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extern int pe4_hal_enable_charger(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool en);
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extern int pe40_hal_get_adapter_output(struct chg_alg_device *alg,
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struct pe4_pps_status *pe4_status);
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extern int pe4_hal_get_vbus(struct chg_alg_device *alg);
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extern int pe4_hal_get_vbat(struct chg_alg_device *alg);
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extern int pe4_hal_get_ibus(struct chg_alg_device *alg, int *ibus);
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extern int pe4_hal_get_ibat(struct chg_alg_device *alg);
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extern int pe4_hal_dump_registers(struct chg_alg_device *alg);
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extern int pe4_hal_set_mivr(struct chg_alg_device *alg,
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enum chg_idx chgidx, int uV);
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extern int pe4_hal_get_mivr(struct chg_alg_device *alg,
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enum chg_idx chgidx, int *mivr1);
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extern int pe4_hal_get_mivr_state(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool *in_loop);
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extern int pe4_hal_charger_enable_chip(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool enable);
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extern int pe4_hal_is_charger_enable(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool *en);
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extern int pe4_hal_get_charging_current(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 *ua);
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extern int pe4_hal_get_min_charging_current(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 *uA);
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extern int pe4_hal_set_eoc_current(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 uA);
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extern int pe4_hal_get_min_input_current(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 *uA);
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extern int pe4_hal_safety_check(struct chg_alg_device *alg,
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int ieoc);
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extern int pe4_hal_set_cv(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 uv);
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extern int pe4_hal_set_cv(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 uv);
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extern int pe4_hal_enable_termination(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool enable);
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extern int pe4_hal_reset_eoc_state(struct chg_alg_device *alg);
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#endif /* __MTK_PE4_H */
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