130 lines
3.2 KiB
C
130 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef __DEVAPC_MT6768_H__
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#define __DEVAPC_MT6768_H__
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/******************************************************************************
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* VARIABLE DEFINATION
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******************************************************************************/
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/* dbg status default setting */
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#define PLAT_DBG_UT_DEFAULT false
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#define PLAT_DBG_KE_DEFAULT true
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#define PLAT_DBG_AEE_DEFAULT true
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#define PLAT_DBG_DAPC_DEFAULT false
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#define PLAT_VIO_CFG_MAX_IDX 242
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#define PLAT_VIO_MAX_IDX 282
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#define PLAT_VIO_MASK_STA_NUM 9
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#define PLAT_VIO_SHIFT_MAX_BIT 21
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/******************************************************************************
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* DATA STRUCTURE & FUNCTION DEFINATION
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******************************************************************************/
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const char *bus_id_to_master(int bus_id, uint32_t vio_addr, int vio_idx);
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const char *index_to_subsys(unsigned int index);
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/* violation index corresponds to subsys */
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enum SMI_INDEX {
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SMI_COMMON = 157,
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SMI_LARB0 = 158,
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IMGSYS_SMI_LARB2 = 182,
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VDECSYS_SMI_LARB1 = 198,
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};
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enum MFGSYS_INDEX {
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MFGSYS_START = 151,
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MFGSYS_END = 154,
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};
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enum MMSYS_INDEX {
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MMSYS_MDP_START = 155,
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MMSYS_MDP_END = 165,
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MMSYS_DISP_START = 166,
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MMSYS_DISP_END = 176,
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};
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enum IMGSYS_INDEX {
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IMGSYS_START = 181,
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IMGSYS_END = 196,
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};
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enum VENCSYS_INDEX {
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VENCSYS_START = 201,
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VENCSYS_END = 208,
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};
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enum VDECSYS_INDEX {
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VDECSYS_START = 197,
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VDECSYS_END = 200,
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};
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enum CAMSYS_INDEX {
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CAMSYS_START = 209,
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CAMSYS_END = 242,
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};
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enum OTHER_TYPES_INDEX {
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SRAMROM_VIO_INDEX = 270,
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TOPAXI_SI0_DECERR = 264,
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PERIAXI_SI1_DECERR = 266,
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};
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enum BUSID_LENGTH {
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PERIAXI_INT_MI_BIT_LENGTH = 4,
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TOPAXI_MI0_BIT_LENGTH = 12,
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};
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/* bit == 2 means don't care */
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struct PERIAXI_ID_INFO {
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const char *master;
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uint8_t bit[PERIAXI_INT_MI_BIT_LENGTH];
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};
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struct TOPAXI_ID_INFO {
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const char *master;
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uint8_t bit[TOPAXI_MI0_BIT_LENGTH];
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};
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/******************************************************************************
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* PLATFORM DEFINATION
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******************************************************************************/
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/* For Infra VIO_DBG */
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#define INFRA_VIO_DBG_MSTID 0x0000FFFF
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#define INFRA_VIO_DBG_MSTID_START_BIT 0
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#define INFRA_VIO_DBG_DMNID 0x003F0000
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#define INFRA_VIO_DBG_DMNID_START_BIT 16
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#define INFRA_VIO_DBG_W_VIO 0x00400000
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#define INFRA_VIO_DBG_W_VIO_START_BIT 22
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#define INFRA_VIO_DBG_R_VIO 0x00800000
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#define INFRA_VIO_DBG_R_VIO_START_BIT 23
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#define INFRA_VIO_ADDR_HIGH 0x0F000000
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#define INFRA_VIO_ADDR_HIGH_START_BIT 24
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/* For SRAMROM VIO */
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#define SRAMROM_SEC_VIO_ID_MASK 0x00FFFF00
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#define SRAMROM_SEC_VIO_ID_SHIFT 8
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#define SRAMROM_SEC_VIO_DOMAIN_MASK 0x0F000000
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#define SRAMROM_SEC_VIO_DOMAIN_SHIFT 24
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#define SRAMROM_SEC_VIO_RW_MASK 0x80000000
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#define SRAMROM_SEC_VIO_RW_SHIFT 31
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/* For DEVAPC PD */
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#define PD_VIO_MASK_OFFSET 0x0
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#define PD_VIO_STA_OFFSET 0x400
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#define PD_VIO_DBG0_OFFSET 0x900
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#define PD_VIO_DBG1_OFFSET 0x904
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#define PD_APC_CON_OFFSET 0xF00
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#define PD_SHIFT_STA_OFFSET 0xF10
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#define PD_SHIFT_SEL_OFFSET 0xF14
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#define PD_SHIFT_CON_OFFSET 0xF20
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#define SRAM_START_ADDR (0x100000)
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#endif /* __DEVAPC_MT6768_H__ */
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