151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _LINUX_MTK_PM_QOS_H
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#define _LINUX_MTK_PM_QOS_H
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enum {
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MTK_PM_QOS_RESERVED = 0,
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MTK_PM_QOS_MEMORY_BANDWIDTH,
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MTK_PM_QOS_MEMORY_EXT_BANDWIDTH,
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MTK_PM_QOS_HRT_BANDWIDTH,
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MTK_PM_QOS_DDR_OPP,
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MTK_PM_QOS_VCORE_OPP,
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MTK_PM_QOS_SCP_VCORE_REQUEST,
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MTK_PM_QOS_VVPU_OPP,
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MTK_PM_QOS_VMDLA_OPP,
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PM_QOS_DISP_FREQ,
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PM_QOS_MDP_FREQ,
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PM_QOS_VDEC_FREQ,
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PM_QOS_VENC_FREQ,
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PM_QOS_IMG_FREQ,
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PM_QOS_CAM_FREQ,
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PM_QOS_DPE_FREQ,
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PM_QOS_MM0_BANDWIDTH_LIMITER,
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PM_QOS_MM1_BANDWIDTH_LIMITER,
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MTK_PM_QOS_CPU_MEMORY_BANDWIDTH,
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MTK_PM_QOS_GPU_MEMORY_BANDWIDTH,
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MTK_PM_QOS_OTHER_MEMORY_BANDWIDTH,
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MTK_PM_QOS_POWER_MODEL_DDR_REQUEST,
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MTK_PM_QOS_POWER_MODEL_VCORE_REQUEST,
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MTK_PM_QOS_VCORE_DVFS_FORCE_OPP,
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MTK_PM_QOS_MEMORY_BANDWIDTH_TEST,
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/* insert new class ID */
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MTK_PM_QOS_NUM_CLASSES,
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};
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#define PM_QOS_ISP_HRT_BANDWIDTH MTK_PM_QOS_HRT_BANDWIDTH
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#define PM_QOS_MM_MEMORY_BANDWIDTH MTK_PM_QOS_MEMORY_BANDWIDTH
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#define PM_QOS_APU_MEMORY_BANDWIDTH MTK_PM_QOS_MEMORY_EXT_BANDWIDTH
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#define MTK_PM_QOS_ISP_HRT_BANDWIDTH PM_QOS_ISP_HRT_BANDWIDTH
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#define MTK_PM_QOS_MM_MEMORY_BANDWIDTH MTK_PM_QOS_MEMORY_BANDWIDTH
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#define MTK_PM_QOS_MEMORY_BANDWIDTH_DEFAULT_VALUE 0
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#define MTK_PM_QOS_HRT_BANDWIDTH_DEFAULT_VALUE 0
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#define MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE 16
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#define MTK_PM_QOS_VCORE_OPP_DEFAULT_VALUE 16
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#define MTK_PM_QOS_SCP_VCORE_REQUEST_DEFAULT_VALUE 16
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#define MTK_PM_QOS_VVPU_OPP_DEFAULT_VALUE 3
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#define MTK_PM_QOS_VMDLA_OPP_DEFAULT_VALUE 3
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#define PM_QOS_MM_FREQ_DEFAULT_VALUE 0
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#define PM_QOS_MM_BANDWIDTH_LIMITER_DEFAULT_VALUE 0
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#define MTK_PM_QOS_POWER_MODEL_DDR_REQUEST_DEFAULT_VALUE 0
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#define MTK_PM_QOS_POWER_MODEL_VCORE_REQUEST_DEFAULT_VALUE 0
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#define MTK_PM_QOS_VCORE_DVFS_FORCE_OPP_DEFAULT_VALUE 32
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#define PM_QOS_ISP_HRT_BANDWIDTH_DEFAULT_VALUE 0
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#define PM_QOS_APU_MEMORY_BANDWIDTH_DEFAULT_VALUE 0
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#define PM_QOS_MM_MEMORY_BANDWIDTH_DEFAULT_VALUE 0
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#if defined(CONFIG_MACH_MT6761) || defined(CONFIG_MACH_MT6765) || defined(CONFIG_MACH_MT6779)
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enum ddr_opp {
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DDR_OPP_0 = 0,
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DDR_OPP_1,
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DDR_OPP_2,
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DDR_OPP_3,
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DDR_OPP_4,
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DDR_OPP_5,
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DDR_OPP_6,
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DDR_OPP_7,
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DDR_OPP_UNREQ = MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE,
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};
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enum vcore_opp {
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VCORE_OPP_0 = 0,
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VCORE_OPP_1,
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VCORE_OPP_2,
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VCORE_OPP_3,
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VCORE_OPP_4,
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VCORE_OPP_5,
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VCORE_OPP_6,
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VCORE_OPP_7,
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VCORE_OPP_UNREQ = MTK_PM_QOS_VCORE_OPP_DEFAULT_VALUE,
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};
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#endif
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struct mtk_pm_qos_request {
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struct list_head list_node;
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struct plist_node node;
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unsigned int pm_qos_class;
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char owner[20];
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};
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#if IS_ENABLED(CONFIG_MTK_PMQOS)
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void mtk_pm_qos_add_request(struct mtk_pm_qos_request *req,
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unsigned int mtk_pm_qos_class, s32 value);
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void mtk_pm_qos_update_request(struct mtk_pm_qos_request *req,
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s32 new_value);
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void mtk_pm_qos_remove_request(struct mtk_pm_qos_request *req);
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int mtk_pm_qos_request(unsigned int mtk_pm_qos_class);
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int mtk_pm_qos_add_notifier(unsigned int mtk_pm_qos_class,
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struct notifier_block *notifier);
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int mtk_pm_qos_remove_notifier(unsigned int mtk_pm_qos_class,
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struct notifier_block *notifier);
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int mtk_pm_qos_request(unsigned int pm_qos_class);
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int mtk_pm_qos_request_active(struct mtk_pm_qos_request *req);
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#else
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static inline void mtk_pm_qos_add_request(struct mtk_pm_qos_request *req,
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unsigned int mtk_pm_qos_class, s32 value)
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{
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}
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static inline void mtk_pm_qos_update_request(
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struct mtk_pm_qos_request *req, s32 new_value)
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{
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}
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static inline void mtk_pm_qos_remove_request(struct mtk_pm_qos_request *req)
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{
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}
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static inline int mtk_pm_qos_request(unsigned int mtk_pm_qos_class)
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{
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return 0;
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}
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static inline int mtk_pm_qos_add_notifier(unsigned int mtk_pm_qos_class,
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struct notifier_block *notifier)
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{
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return 0;
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}
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static inline int mtk_pm_qos_remove_notifier(unsigned int mtk_pm_qos_class,
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struct notifier_block *notifier)
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{
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return 0;
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}
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static inline int mtk_pm_qos_request_active(struct mtk_pm_qos_request *req)
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{
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return 0;
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}
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#endif
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#endif
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