931 lines
23 KiB
C
931 lines
23 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _UAPI_MEDIATEK_DRM_H
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#define _UAPI_MEDIATEK_DRM_H
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#include <drm/drm.h>
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#define MTK_SUBMIT_NO_IMPLICIT 0x0 /* disable implicit sync */
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#define MTK_SUBMIT_IN_FENCE 0x1 /* enable input fence */
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#define MTK_SUBMIT_OUT_FENCE 0x2 /* enable output fence */
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#define MTK_DRM_PROP_OVERLAP_LAYER_NUM "OVERLAP_LAYER_NUM"
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#define MTK_DRM_PROP_NEXT_BUFF_IDX "NEXT_BUFF_IDX"
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#define MTK_DRM_PROP_PRESENT_FENCE "PRESENT_FENCE"
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#define MTK_DRM_PROP_OVL_DSI_SEQ "OVL_DSI_SEQ"
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struct mml_frame_info;
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/**
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* User-desired buffer creation information structure.
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*
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* @size: user-desired memory allocation size.
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* - this size value would be page-aligned internally.
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* @flags: user request for setting memory type or cache attributes.
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* @handle: returned a handle to created gem object.
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* - this handle will be set by gem module of kernel side.
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*/
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struct drm_mtk_gem_create {
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uint64_t size;
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uint32_t flags;
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uint32_t handle;
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};
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/**
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* A structure for getting buffer offset.
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*
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* @handle: a pointer to gem object created.
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* @pad: just padding to be 64-bit aligned.
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* @offset: relatived offset value of the memory region allocated.
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* - this value should be set by user.
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*/
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struct drm_mtk_gem_map_off {
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uint32_t handle;
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uint32_t pad;
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uint64_t offset;
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};
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/**
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* A structure for buffer submit.
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*
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* @type:
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* @session_id:
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* @layer_id:
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* @layer_en:
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* @fb_id:
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* @index:
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* @fence_fd:
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* @interface_index:
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* @interface_fence_fd:
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*/
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struct drm_mtk_gem_submit {
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uint32_t type;
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/* session */
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uint32_t session_id;
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/* layer */
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uint32_t layer_id;
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uint32_t layer_en;
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/* buffer */
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uint32_t fb_id;
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/* output */
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uint32_t index;
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int32_t fence_fd;
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uint32_t interface_index;
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int32_t interface_fence_fd;
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int32_t ion_fd;
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};
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/**
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* A structure for secure/gem hnd transform.
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*
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* @sec_hnd: handle of secure memory
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* @gem_hnd: handle of gem
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*/
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struct drm_mtk_sec_gem_hnd {
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uint32_t sec_hnd;
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uint32_t gem_hnd;
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};
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/**
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* A structure for session create.
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*
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* @type:
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* @device_id:
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* @mode:
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* @session_id:
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*/
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struct drm_mtk_session {
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uint32_t type;
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/* device */
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uint32_t device_id;
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/* mode */
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uint32_t mode;
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/* output */
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uint32_t session_id;
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};
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/**
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* A structure for session create.
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*
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* @level_id: id
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* @level_fps: fps
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* @max_fps: max fps
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* @min_fps: min fps
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*/
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struct msync_level_table {
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unsigned int level_id;
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unsigned int level_fps;
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unsigned int max_fps;
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unsigned int min_fps;
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};
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/**
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* A structure for session create.
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*
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* @msync_max_fps: max fps
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* @msync_min_fps: min fps
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* @msync_level_num: level number
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* @level_tb: A pointer of level table
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*/
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struct msync_parameter_table {
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unsigned int msync_max_fps;
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unsigned int msync_min_fps;
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unsigned int msync_level_num;
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struct msync_level_table *level_tb;
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};
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/* PQ */
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#define C_TUN_IDX 19 /* COLOR_TUNING_INDEX */
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#define COLOR_TUNING_INDEX 19
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#define THSHP_TUNING_INDEX 24
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#define THSHP_PARAM_MAX 146 /* TDSHP_3_0 */
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#define PARTIAL_Y_INDEX 22
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#define GLOBAL_SAT_SIZE 22
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#define CONTRAST_SIZE 22
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#define BRIGHTNESS_SIZE 22
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#define PARTIAL_Y_SIZE 16
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#define PQ_HUE_ADJ_PHASE_CNT 4
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#define PQ_SAT_ADJ_PHASE_CNT 4
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#define PQ_PARTIALS_CONTROL 5
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#define PURP_TONE_SIZE 3
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#define SKIN_TONE_SIZE 8 /* (-6) */
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#define GRASS_TONE_SIZE 6 /* (-2) */
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#define SKY_TONE_SIZE 3
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#define CCORR_COEF_CNT 4 /* ccorr feature */
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#define S_GAIN_BY_Y_CONTROL_CNT 5
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#define S_GAIN_BY_Y_HUE_PHASE_CNT 20
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#define LSP_CONTROL_CNT 8
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#define COLOR_3D_CNT 4 /* color 3D feature */
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#define COLOR_3D_WINDOW_CNT 3
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#define COLOR_3D_WINDOW_SIZE 45
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#define C_3D_CNT 4 /* COLOR_3D_CNT */
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#define C_3D_WINDOW_CNT 3
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#define C_3D_WINDOW_SIZE 45
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enum TONE_ENUM { PURP_TONE = 0, SKIN_TONE = 1, GRASS_TONE = 2, SKY_TONE = 3 };
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struct DISP_PQ_WIN_PARAM {
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int split_en;
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int start_x;
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int start_y;
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int end_x;
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int end_y;
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};
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#define DISP_PQ_WIN_PARAM_T struct DISP_PQ_WIN_PARAM
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struct DISP_PQ_MAPPING_PARAM {
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int image;
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int video;
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int camera;
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};
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#define DISP_PQ_MAPPING_PARAM_T struct DISP_PQ_MAPPING_PARAM
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struct MDP_COLOR_CAP {
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unsigned int en;
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unsigned int pos_x;
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unsigned int pos_y;
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};
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struct MDP_TDSHP_REG {
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unsigned int TDS_GAIN_MID;
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unsigned int TDS_GAIN_HIGH;
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unsigned int TDS_COR_GAIN;
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unsigned int TDS_COR_THR;
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unsigned int TDS_COR_ZERO;
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unsigned int TDS_GAIN;
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unsigned int TDS_COR_VALUE;
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};
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struct DISPLAY_PQ_T {
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unsigned int GLOBAL_SAT[GLOBAL_SAT_SIZE];
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unsigned int CONTRAST[CONTRAST_SIZE];
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unsigned int BRIGHTNESS[BRIGHTNESS_SIZE];
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unsigned int PARTIAL_Y[PARTIAL_Y_INDEX][PARTIAL_Y_SIZE];
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unsigned int PURP_TONE_S[COLOR_TUNING_INDEX]
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[PQ_PARTIALS_CONTROL][PURP_TONE_SIZE];
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unsigned int SKIN_TONE_S[COLOR_TUNING_INDEX]
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[PQ_PARTIALS_CONTROL][SKIN_TONE_SIZE];
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unsigned int GRASS_TONE_S[COLOR_TUNING_INDEX]
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[PQ_PARTIALS_CONTROL][GRASS_TONE_SIZE];
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unsigned int SKY_TONE_S[COLOR_TUNING_INDEX]
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[PQ_PARTIALS_CONTROL][SKY_TONE_SIZE];
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unsigned int PURP_TONE_H[COLOR_TUNING_INDEX][PURP_TONE_SIZE];
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unsigned int SKIN_TONE_H[COLOR_TUNING_INDEX][SKIN_TONE_SIZE];
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unsigned int GRASS_TONE_H[COLOR_TUNING_INDEX][GRASS_TONE_SIZE];
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unsigned int SKY_TONE_H[COLOR_TUNING_INDEX][SKY_TONE_SIZE];
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unsigned int CCORR_COEF[CCORR_COEF_CNT][3][3];
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unsigned int S_GAIN_BY_Y[5][S_GAIN_BY_Y_HUE_PHASE_CNT];
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unsigned int S_GAIN_BY_Y_EN;
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unsigned int LSP_EN;
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unsigned int LSP[LSP_CONTROL_CNT];
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unsigned int COLOR_3D[4][COLOR_3D_WINDOW_CNT][COLOR_3D_WINDOW_SIZE];
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};
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#define DISPLAY_PQ struct DISPLAY_PQ_T
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struct DISPLAY_COLOR_REG {
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unsigned int GLOBAL_SAT;
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unsigned int CONTRAST;
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unsigned int BRIGHTNESS;
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unsigned int PARTIAL_Y[PARTIAL_Y_SIZE];
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unsigned int PURP_TONE_S[PQ_PARTIALS_CONTROL][PURP_TONE_SIZE];
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unsigned int SKIN_TONE_S[PQ_PARTIALS_CONTROL][SKIN_TONE_SIZE];
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unsigned int GRASS_TONE_S[PQ_PARTIALS_CONTROL][GRASS_TONE_SIZE];
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unsigned int SKY_TONE_S[PQ_PARTIALS_CONTROL][SKY_TONE_SIZE];
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unsigned int PURP_TONE_H[PURP_TONE_SIZE];
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unsigned int SKIN_TONE_H[SKIN_TONE_SIZE];
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unsigned int GRASS_TONE_H[GRASS_TONE_SIZE];
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unsigned int SKY_TONE_H[SKY_TONE_SIZE];
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unsigned int S_GAIN_BY_Y[S_GAIN_BY_Y_CONTROL_CNT]
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[S_GAIN_BY_Y_HUE_PHASE_CNT];
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unsigned int S_GAIN_BY_Y_EN;
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unsigned int LSP_EN;
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unsigned int COLOR_3D[COLOR_3D_WINDOW_CNT][COLOR_3D_WINDOW_SIZE];
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};
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#define DISPLAY_COLOR_REG_T struct DISPLAY_COLOR_REG
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#define DISP_COLOR_TM_MAX 4
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struct DISP_COLOR_TRANSFORM {
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int matrix[DISP_COLOR_TM_MAX][DISP_COLOR_TM_MAX];
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};
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struct DISPLAY_TDSHP_T {
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unsigned int entry[THSHP_TUNING_INDEX][THSHP_PARAM_MAX];
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};
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#define DISPLAY_TDSHP struct DISPLAY_TDSHP_T
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enum PQ_DS_index_t {
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DS_en = 0,
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iUpSlope,
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iUpThreshold,
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iDownSlope,
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iDownThreshold,
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iISO_en,
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iISO_thr1,
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iISO_thr0,
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iISO_thr3,
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iISO_thr2,
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iISO_IIR_alpha,
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iCorZero_clip2,
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iCorZero_clip1,
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iCorZero_clip0,
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iCorThr_clip2,
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iCorThr_clip1,
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iCorThr_clip0,
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iCorGain_clip2,
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iCorGain_clip1,
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iCorGain_clip0,
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iGain_clip2,
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iGain_clip1,
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iGain_clip0,
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PQ_DS_INDEX_MAX
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};
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struct DISP_PQ_DS_PARAM {
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int param[PQ_DS_INDEX_MAX];
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};
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#define DISP_PQ_DS_PARAM_T struct DISP_PQ_DS_PARAM
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enum PQ_DC_index_t {
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BlackEffectEnable = 0,
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WhiteEffectEnable,
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StrongBlackEffect,
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StrongWhiteEffect,
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AdaptiveBlackEffect,
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AdaptiveWhiteEffect,
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ScenceChangeOnceEn,
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ScenceChangeControlEn,
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ScenceChangeControl,
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ScenceChangeTh1,
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ScenceChangeTh2,
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ScenceChangeTh3,
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ContentSmooth1,
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ContentSmooth2,
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ContentSmooth3,
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MiddleRegionGain1,
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MiddleRegionGain2,
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BlackRegionGain1,
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BlackRegionGain2,
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BlackRegionRange,
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BlackEffectLevel,
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BlackEffectParam1,
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BlackEffectParam2,
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BlackEffectParam3,
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BlackEffectParam4,
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WhiteRegionGain1,
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WhiteRegionGain2,
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WhiteRegionRange,
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WhiteEffectLevel,
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WhiteEffectParam1,
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WhiteEffectParam2,
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WhiteEffectParam3,
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WhiteEffectParam4,
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ContrastAdjust1,
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ContrastAdjust2,
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DCChangeSpeedLevel,
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ProtectRegionEffect,
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DCChangeSpeedLevel2,
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ProtectRegionWeight,
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DCEnable,
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DarkSceneTh,
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DarkSceneSlope,
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DarkDCGain,
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DarkACGain,
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BinomialTh,
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BinomialSlope,
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BinomialDCGain,
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BinomialACGain,
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BinomialTarRange,
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bIIRCurveDiffSumTh,
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bIIRCurveDiffMaxTh,
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bGlobalPQEn,
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bHistAvoidFlatBgEn,
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PQDC_INDEX_MAX
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};
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#define PQ_DC_index enum PQ_DC_index_t
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struct DISP_PQ_DC_PARAM {
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int param[PQDC_INDEX_MAX];
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};
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/* OD */
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struct DISP_OD_CMD {
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unsigned int size;
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unsigned int type;
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unsigned int ret;
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unsigned long param0;
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unsigned long param1;
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unsigned long param2;
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unsigned long param3;
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};
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struct DISP_WRITE_REG {
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unsigned int reg;
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unsigned int val;
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unsigned int mask;
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};
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struct DISP_READ_REG {
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unsigned int reg;
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unsigned int val;
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unsigned int mask;
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};
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enum disp_ccorr_id_t {
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DISP_CCORR0 = 0,
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DISP_CCORR1,
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DISP_CCORR_TOTAL
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};
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struct DISP_CCORR_COEF_T {
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enum disp_ccorr_id_t hw_id;
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unsigned int coef[3][3];
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};
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#define DISP_GAMMA_LUT_SIZE 512
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enum disp_gamma_id_t {
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DISP_GAMMA0 = 0,
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DISP_GAMMA1,
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DISP_GAMMA_TOTAL
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};
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struct DISP_GAMMA_LUT_T {
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enum disp_gamma_id_t hw_id;
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unsigned int lut[DISP_GAMMA_LUT_SIZE];
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};
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struct DISP_PQ_PARAM {
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unsigned int u4SHPGain; /* 0 : min , 9 : max. */
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unsigned int u4SatGain; /* 0 : min , 9 : max. */
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unsigned int u4PartialY; /* 0 : min , 9 : max. */
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unsigned int u4HueAdj[PQ_HUE_ADJ_PHASE_CNT];
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unsigned int u4SatAdj[PQ_SAT_ADJ_PHASE_CNT];
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unsigned int u4Contrast; /* 0 : min , 9 : max. */
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unsigned int u4Brightness; /* 0 : min , 9 : max. */
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unsigned int u4Ccorr; /* 0 : min , 3 : max. ccorr feature */
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unsigned int u4ColorLUT; /* 0 : min , 3 : max. ccorr feature */
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};
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#define DISP_PQ_PARAM_T struct DISP_PQ_PARAM
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#define DRM_MTK_GEM_CREATE 0x00
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#define DRM_MTK_GEM_MAP_OFFSET 0x01
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#define DRM_MTK_GEM_SUBMIT 0x02
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#define DRM_MTK_SESSION_CREATE 0x03
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#define DRM_MTK_SESSION_DESTROY 0x04
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#define DRM_MTK_LAYERING_RULE 0x05
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#define DRM_MTK_CRTC_GETFENCE 0x06
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#define DRM_MTK_WAIT_REPAINT 0x07
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#define DRM_MTK_GET_DISPLAY_CAPS 0x08
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#define DRM_MTK_SET_DDP_MODE 0x09
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#define DRM_MTK_GET_SESSION_INFO 0x0A
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#define DRM_MTK_SEC_HND_TO_GEM_HND 0x0B
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#define DRM_MTK_GET_MASTER_INFO 0x0C
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#define DRM_MTK_CRTC_GETSFFENCE 0x0D
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#define DRM_MTK_MML_GEM_SUBMIT 0x0E
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#define DRM_MTK_SET_MSYNC_PARAMS 0x0F
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#define DRM_MTK_GET_MSYNC_PARAMS 0x10
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#define DRM_MTK_FACTORY_LCM_AUTO_TEST 0x11
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/* PQ */
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#define DRM_MTK_PQ_PERSIST_PROPERTY 0x1F
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#define DRM_MTK_SET_CCORR 0x20
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#define DRM_MTK_CCORR_EVENTCTL 0x21
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#define DRM_MTK_CCORR_GET_IRQ 0x22
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#define DRM_MTK_SET_GAMMALUT 0x23
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#define DRM_MTK_SET_PQPARAM 0x24
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#define DRM_MTK_SET_PQINDEX 0x25
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#define DRM_MTK_SET_COLOR_REG 0x26
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#define DRM_MTK_MUTEX_CONTROL 0x27
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#define DRM_MTK_READ_REG 0x28
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#define DRM_MTK_WRITE_REG 0x29
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#define DRM_MTK_BYPASS_COLOR 0x2A
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#define DRM_MTK_PQ_SET_WINDOW 0x2B
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#define DRM_MTK_GET_LCM_INDEX 0x2C
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#define DRM_MTK_SUPPORT_COLOR_TRANSFORM 0x2D
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#define DRM_MTK_READ_SW_REG 0x2E
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#define DRM_MTK_WRITE_SW_REG 0x2F
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/* AAL */
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#define DRM_MTK_AAL_INIT_REG 0x30
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#define DRM_MTK_AAL_GET_HIST 0x31
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#define DRM_MTK_AAL_SET_PARAM 0x32
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#define DRM_MTK_AAL_EVENTCTL 0x33
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#define DRM_MTK_AAL_INIT_DRE30 0x34
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#define DRM_MTK_AAL_GET_SIZE 0x35
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#define DRM_MTK_HDMI_GET_DEV_INFO 0x3A
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#define DRM_MTK_HDMI_AUDIO_ENABLE 0x3B
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#define DRM_MTK_HDMI_AUDIO_CONFIG 0x3C
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#define DRM_MTK_HDMI_GET_CAPABILITY 0x3D
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#define DRM_MTK_DEBUG_LOG 0x3E
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enum MTKFB_DISPIF_TYPE {
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DISPIF_TYPE_DBI = 0,
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DISPIF_TYPE_DPI,
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DISPIF_TYPE_DSI,
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DISPIF_TYPE_DPI0,
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DISPIF_TYPE_DPI1,
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DISPIF_TYPE_DSI0,
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DISPIF_TYPE_DSI1,
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HDMI = 7,
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HDMI_SMARTBOOK,
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MHL,
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DISPIF_TYPE_EPD,
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DISPLAYPORT,
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SLIMPORT
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};
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enum MTKFB_DISPIF_MODE {
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DISPIF_MODE_VIDEO = 0,
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DISPIF_MODE_COMMAND
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};
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struct mtk_dispif_info {
|
|
unsigned int display_id;
|
|
unsigned int isHwVsyncAvailable;
|
|
enum MTKFB_DISPIF_TYPE displayType;
|
|
unsigned int displayWidth;
|
|
unsigned int displayHeight;
|
|
unsigned int displayFormat;
|
|
enum MTKFB_DISPIF_MODE displayMode;
|
|
unsigned int vsyncFPS;
|
|
unsigned int physicalWidth;
|
|
unsigned int physicalHeight;
|
|
unsigned int isConnected;
|
|
unsigned int lcmOriginalWidth;
|
|
unsigned int lcmOriginalHeight;
|
|
};
|
|
|
|
#define DRM_IOCTL_MTK_SET_DDP_MODE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SET_DDP_MODE, unsigned int)
|
|
|
|
enum MTK_DRM_SESSION_MODE {
|
|
MTK_DRM_SESSION_INVALID = 0,
|
|
/* single output */
|
|
MTK_DRM_SESSION_DL,
|
|
|
|
/* two ouputs */
|
|
MTK_DRM_SESSION_DOUBLE_DL,
|
|
MTK_DRM_SESSION_DC_MIRROR,
|
|
|
|
/* three session at same time */
|
|
MTK_DRM_SESSION_TRIPLE_DL,
|
|
MTK_DRM_SESSION_NUM,
|
|
};
|
|
|
|
enum MTK_LAYERING_CAPS {
|
|
MTK_LAYERING_OVL_ONLY = 0x00000001,
|
|
MTK_MDP_RSZ_LAYER = 0x00000002,
|
|
MTK_DISP_RSZ_LAYER = 0x00000004,
|
|
MTK_MDP_ROT_LAYER = 0x00000008,
|
|
MTK_MDP_HDR_LAYER = 0x00000010,
|
|
MTK_NO_FBDC = 0x00000020,
|
|
MTK_CLIENT_CLEAR_LAYER = 0x00000040,
|
|
MTK_DISP_CLIENT_CLEAR_LAYER = 0x00000080,
|
|
MTK_DMDP_RSZ_LAYER = 0x00000100,
|
|
MTK_MML_OVL_LAYER = 0x00000200,
|
|
MTK_MML_DISP_DIRECT_LINK_LAYER = 0x00000400,
|
|
MTK_MML_DISP_DIRECT_DECOUPLE_LAYER = 0x00000800,
|
|
MTK_MML_DISP_DECOUPLE_LAYER = 0x00001000,
|
|
MTK_MML_DISP_MDP_LAYER = 0x00002000,
|
|
MTK_MML_DISP_NOT_SUPPORT = 0x00004000,
|
|
};
|
|
|
|
struct drm_mtk_layer_config {
|
|
uint32_t ovl_id;
|
|
uint32_t src_fmt;
|
|
int dataspace;
|
|
uint32_t dst_offset_x, dst_offset_y;
|
|
uint32_t dst_width, dst_height;
|
|
int ext_sel_layer;
|
|
uint32_t src_offset_x, src_offset_y;
|
|
uint32_t src_width, src_height;
|
|
uint32_t layer_caps;
|
|
uint32_t clip; /* drv internal use */
|
|
__u8 compress;
|
|
__u8 secure;
|
|
};
|
|
|
|
struct drm_mtk_layering_info {
|
|
struct drm_mtk_layer_config __user *input_config[3];
|
|
int disp_mode[3];
|
|
/* index of crtc display mode including resolution, fps... */
|
|
int disp_mode_idx[3];
|
|
int layer_num[3];
|
|
int gles_head[3];
|
|
int gles_tail[3];
|
|
int hrt_num;
|
|
/* res_idx: SF/HWC selects which resolution to use */
|
|
int res_idx;
|
|
uint32_t hrt_weight;
|
|
uint32_t hrt_idx;
|
|
struct mml_frame_info *mml_cfg[3];
|
|
};
|
|
|
|
/**
|
|
* A structure for fence retrival.
|
|
*
|
|
* @crtc_id:
|
|
* @fence_fd:
|
|
* @fence_idx:
|
|
*/
|
|
struct drm_mtk_fence {
|
|
/* input */
|
|
uint32_t crtc_id; /**< Id */
|
|
|
|
/* output */
|
|
int32_t fence_fd;
|
|
/* device */
|
|
uint32_t fence_idx;
|
|
};
|
|
|
|
enum DRM_REPAINT_TYPE {
|
|
DRM_WAIT_FOR_REPAINT,
|
|
DRM_REPAINT_FOR_ANTI_LATENCY,
|
|
DRM_REPAINT_FOR_SWITCH_DECOUPLE,
|
|
DRM_REPAINT_FOR_SWITCH_DECOUPLE_MIRROR,
|
|
DRM_REPAINT_FOR_IDLE,
|
|
DRM_REPAINT_TYPE_NUM,
|
|
};
|
|
|
|
enum MTK_DRM_DISP_FEATURE {
|
|
DRM_DISP_FEATURE_HRT = 0x00000001,
|
|
DRM_DISP_FEATURE_DISP_SELF_REFRESH = 0x00000002,
|
|
DRM_DISP_FEATURE_RPO = 0x00000004,
|
|
DRM_DISP_FEATURE_FORCE_DISABLE_AOD = 0x00000008,
|
|
DRM_DISP_FEATURE_OUTPUT_ROTATED = 0x00000010,
|
|
DRM_DISP_FEATURE_THREE_SESSION = 0x00000020,
|
|
DRM_DISP_FEATURE_FBDC = 0x00000040,
|
|
DRM_DISP_FEATURE_SF_PRESENT_FENCE = 0x00000080,
|
|
DRM_DISP_FEATURE_PQ_34_COLOR_MATRIX = 0x00000100,
|
|
/*Msync*/
|
|
DRM_DISP_FEATURE_MSYNC2_0 = 0x00000200,
|
|
DRM_DISP_FEATURE_MML_PRIMARY = 0x00000400,
|
|
};
|
|
|
|
enum mtk_mmsys_id {
|
|
MMSYS_MT2701 = 0x2701,
|
|
MMSYS_MT2712 = 0x2712,
|
|
MMSYS_MT8173 = 0x8173,
|
|
MMSYS_MT6779 = 0x6779,
|
|
MMSYS_MT6885 = 0x6885,
|
|
MMSYS_MT6983 = 0x6983,
|
|
MMSYS_MT6873 = 0x6873,
|
|
MMSYS_MT6853 = 0x6853,
|
|
MMSYS_MT6833 = 0x6833,
|
|
MMSYS_MT6877 = 0x6877,
|
|
MMSYS_MT6879 = 0x6879,
|
|
MMSYS_MT6781 = 0x6781,
|
|
MMSYS_MT6895 = 0x6895,
|
|
MMSYS_MAX,
|
|
};
|
|
|
|
struct mtk_drm_disp_caps_info {
|
|
unsigned int hw_ver;
|
|
unsigned int disp_feature_flag;
|
|
int lcm_degree; /* for rotate180 */
|
|
unsigned int rsz_in_max[2]; /* for RPO { width, height } */
|
|
|
|
/* for WCG */
|
|
int lcm_color_mode;
|
|
unsigned int max_luminance;
|
|
unsigned int average_luminance;
|
|
unsigned int min_luminance;
|
|
|
|
/* Msync2.0 */
|
|
unsigned int msync_level_num;
|
|
};
|
|
|
|
struct drm_mtk_session_info {
|
|
unsigned int session_id;
|
|
unsigned int vsyncFPS;
|
|
unsigned int physicalWidthUm;
|
|
unsigned int physicalHeightUm;
|
|
};
|
|
|
|
enum drm_disp_ccorr_id_t {
|
|
DRM_DISP_CCORR0 = 0,
|
|
DRM_DISP_CCORR1,
|
|
DRM_DISP_CCORR_TOTAL
|
|
};
|
|
|
|
struct DRM_DISP_CCORR_COEF_T {
|
|
enum drm_disp_ccorr_id_t hw_id;
|
|
unsigned int coef[3][3];
|
|
unsigned int offset[3];
|
|
int FinalBacklight;
|
|
int silky_bright_flag;
|
|
};
|
|
|
|
enum drm_disp_gamma_id_t {
|
|
DRM_DISP_GAMMA0 = 0,
|
|
DRM_DISP_GAMMA1,
|
|
DRM_DISP_GAMMA_TOTAL
|
|
};
|
|
|
|
#define DRM_DISP_GAMMA_LUT_SIZE 512
|
|
|
|
struct DRM_DISP_GAMMA_LUT_T {
|
|
enum drm_disp_gamma_id_t hw_id;
|
|
unsigned int lut[DRM_DISP_GAMMA_LUT_SIZE];
|
|
};
|
|
|
|
struct DRM_DISP_READ_REG {
|
|
unsigned int reg;
|
|
unsigned int val;
|
|
unsigned int mask;
|
|
};
|
|
|
|
struct DRM_DISP_WRITE_REG {
|
|
unsigned int reg;
|
|
unsigned int val;
|
|
unsigned int mask;
|
|
};
|
|
|
|
#define DRM_IOCTL_MTK_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_GEM_CREATE, struct drm_mtk_gem_create)
|
|
|
|
#define DRM_IOCTL_MTK_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_GEM_MAP_OFFSET, struct drm_mtk_gem_map_off)
|
|
|
|
#define DRM_IOCTL_MTK_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_GEM_SUBMIT, struct drm_mtk_gem_submit)
|
|
|
|
#define DRM_IOCTL_MTK_SESSION_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SESSION_CREATE, struct drm_mtk_session)
|
|
|
|
#define DRM_IOCTL_MTK_SESSION_DESTROY DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SESSION_DESTROY, struct drm_mtk_session)
|
|
|
|
#define DRM_IOCTL_MTK_LAYERING_RULE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_LAYERING_RULE, struct drm_mtk_layering_info)
|
|
|
|
#define DRM_IOCTL_MTK_CRTC_GETFENCE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_CRTC_GETFENCE, struct drm_mtk_fence)
|
|
|
|
#define DRM_IOCTL_MTK_CRTC_GETSFFENCE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_CRTC_GETSFFENCE, struct drm_mtk_fence)
|
|
|
|
#define DRM_IOCTL_MTK_SET_MSYNC_PARAMS DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SET_MSYNC_PARAMS, struct msync_parameter_table)
|
|
|
|
#define DRM_IOCTL_MTK_GET_MSYNC_PARAMS DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_GET_MSYNC_PARAMS, struct msync_parameter_table)
|
|
|
|
#define DRM_IOCTL_MTK_WAIT_REPAINT DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_WAIT_REPAINT, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_GET_DISPLAY_CAPS DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_GET_DISPLAY_CAPS, struct mtk_drm_disp_caps_info)
|
|
|
|
#define DRM_IOCTL_MTK_SET_DDP_MODE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SET_DDP_MODE, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_GET_SESSION_INFO DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_GET_SESSION_INFO, struct drm_mtk_session_info)
|
|
|
|
#define DRM_IOCTL_MTK_GET_MASTER_INFO DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_GET_MASTER_INFO, int)
|
|
|
|
#define DRM_IOCTL_MTK_SEC_HND_TO_GEM_HND DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SEC_HND_TO_GEM_HND, struct drm_mtk_sec_gem_hnd)
|
|
|
|
#define DRM_IOCTL_MTK_PQ_PERSIST_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_PQ_PERSIST_PROPERTY, unsigned int [32])
|
|
|
|
#define DRM_IOCTL_MTK_SET_CCORR DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SET_CCORR, struct DRM_DISP_CCORR_COEF_T)
|
|
|
|
#define DRM_IOCTL_MTK_CCORR_EVENTCTL DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_CCORR_EVENTCTL, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_CCORR_GET_IRQ DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_CCORR_GET_IRQ, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_SET_GAMMALUT DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SET_GAMMALUT, struct DISP_GAMMA_LUT_T)
|
|
|
|
#define DRM_IOCTL_MTK_SET_PQPARAM DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SET_PQPARAM, struct DISP_PQ_PARAM)
|
|
|
|
#define DRM_IOCTL_MTK_SET_PQINDEX DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SET_PQINDEX, struct DISPLAY_PQ_T)
|
|
|
|
#define DRM_IOCTL_MTK_SET_COLOR_REG DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SET_COLOR_REG, struct DISPLAY_COLOR_REG)
|
|
|
|
#define DRM_IOCTL_MTK_MUTEX_CONTROL DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_MUTEX_CONTROL, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_READ_REG DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_READ_REG, struct DISP_READ_REG)
|
|
|
|
#define DRM_IOCTL_MTK_WRITE_REG DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_WRITE_REG, struct DISP_WRITE_REG)
|
|
|
|
#define DRM_IOCTL_MTK_BYPASS_COLOR DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_BYPASS_COLOR, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_PQ_SET_WINDOW DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_PQ_SET_WINDOW, struct DISP_PQ_WIN_PARAM)
|
|
|
|
#define DRM_IOCTL_MTK_GET_LCM_INDEX DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_GET_LCM_INDEX, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_SUPPORT_COLOR_TRANSFORM DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SUPPORT_COLOR_TRANSFORM, struct DISP_COLOR_TRANSFORM)
|
|
|
|
#define DRM_IOCTL_MTK_READ_SW_REG DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_READ_SW_REG, struct DISP_READ_REG)
|
|
|
|
#define DRM_IOCTL_MTK_WRITE_SW_REG DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_WRITE_SW_REG, struct DISP_WRITE_REG)
|
|
|
|
#define DRM_IOCTL_MTK_SUPPORT_COLOR_TRANSFORM DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_SUPPORT_COLOR_TRANSFORM, \
|
|
struct DISP_COLOR_TRANSFORM)
|
|
|
|
#define DRM_IOCTL_MTK_DEBUG_LOG DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_DEBUG_LOG, int)
|
|
|
|
|
|
/* AAL IOCTL */
|
|
#define AAL_HIST_BIN 33 /* [0..32] */
|
|
#define AAL_DRE_POINT_NUM 29
|
|
#define AAL_DRE_BLK_NUM (16)
|
|
|
|
struct DISP_AAL_INITREG {
|
|
/* DRE */
|
|
int dre_map_bypass;
|
|
/* ESS */
|
|
int cabc_gainlmt[33];
|
|
/* DRE 3.0 Reg. */
|
|
int dre_s_lower;
|
|
int dre_s_upper;
|
|
int dre_y_lower;
|
|
int dre_y_upper;
|
|
int dre_h_lower;
|
|
int dre_h_upper;
|
|
int dre_h_slope;
|
|
int dre_s_slope;
|
|
int dre_y_slope;
|
|
int dre_x_alpha_base;
|
|
int dre_x_alpha_shift_bit;
|
|
int dre_y_alpha_base;
|
|
int dre_y_alpha_shift_bit;
|
|
int act_win_x_end;
|
|
int dre_blk_x_num;
|
|
int dre_blk_y_num;
|
|
int dre_blk_height;
|
|
int dre_blk_width;
|
|
int dre_blk_area;
|
|
int dre_blk_area_min;
|
|
int hist_bin_type;
|
|
int dre_flat_length_slope;
|
|
int dre_flat_length_th;
|
|
int act_win_y_start;
|
|
int act_win_y_end;
|
|
int blk_num_x_start;
|
|
int blk_num_x_end;
|
|
int dre0_blk_num_x_start;
|
|
int dre0_blk_num_x_end;
|
|
int dre1_blk_num_x_start;
|
|
int dre1_blk_num_x_end;
|
|
int blk_cnt_x_start;
|
|
int blk_cnt_x_end;
|
|
int blk_num_y_start;
|
|
int blk_num_y_end;
|
|
int blk_cnt_y_start;
|
|
int blk_cnt_y_end;
|
|
int last_tile_x_flag;
|
|
int last_tile_y_flag;
|
|
};
|
|
|
|
struct DISP_AAL_PARAM {
|
|
int DREGainFltStatus[AAL_DRE_POINT_NUM];
|
|
int cabc_fltgain_force; /* 10-bit ; [0,1023] */
|
|
int cabc_gainlmt[33];
|
|
int FinalBacklight; /* 10-bit ; [0,1023] */
|
|
int silky_bright_flag;
|
|
int allowPartial;
|
|
int refreshLatency; /* DISP_AAL_REFRESH_LATENCY */
|
|
unsigned int silky_bright_gain[3]; /* 13-bit ; [1,8192] */
|
|
unsigned long long dre30_gain;
|
|
};
|
|
|
|
struct DISP_DRE30_INIT {
|
|
/* DRE 3.0 SW */
|
|
unsigned long long dre30_hist_addr;
|
|
};
|
|
|
|
struct DISP_AAL_DISPLAY_SIZE {
|
|
int width;
|
|
int height;
|
|
bool isdualpipe;
|
|
};
|
|
|
|
struct DISP_AAL_HIST {
|
|
unsigned int serviceFlags;
|
|
int backlight;
|
|
int aal0_colorHist;
|
|
int aal1_colorHist;
|
|
unsigned int aal0_maxHist[AAL_HIST_BIN];
|
|
unsigned int aal1_maxHist[AAL_HIST_BIN];
|
|
int requestPartial;
|
|
unsigned long long dre30_hist;
|
|
unsigned int panel_type;
|
|
int essStrengthIndex;
|
|
int ess_enable;
|
|
int dre_enable;
|
|
unsigned int aal0_yHist[AAL_HIST_BIN];
|
|
unsigned int aal1_yHist[AAL_HIST_BIN];
|
|
unsigned int MaxHis_denominator_pipe0[AAL_DRE_BLK_NUM];
|
|
unsigned int MaxHis_denominator_pipe1[AAL_DRE_BLK_NUM];
|
|
};
|
|
|
|
#define DRM_IOCTL_MTK_AAL_INIT_REG DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_AAL_INIT_REG, struct DISP_AAL_INITREG)
|
|
|
|
#define DRM_IOCTL_MTK_AAL_GET_HIST DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_AAL_GET_HIST, struct DISP_AAL_HIST)
|
|
|
|
#define DRM_IOCTL_MTK_AAL_SET_PARAM DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_AAL_SET_PARAM, struct DISP_AAL_PARAM)
|
|
|
|
#define DRM_IOCTL_MTK_AAL_EVENTCTL DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_AAL_EVENTCTL, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_AAL_INIT_DRE30 DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_AAL_INIT_DRE30, struct DISP_DRE30_INIT)
|
|
|
|
#define DRM_IOCTL_MTK_AAL_GET_SIZE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_AAL_GET_SIZE, struct DISP_AAL_DISPLAY_SIZE)
|
|
|
|
#define DRM_IOCTL_MTK_HDMI_GET_DEV_INFO DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_HDMI_GET_DEV_INFO, struct mtk_dispif_info)
|
|
#define DRM_IOCTL_MTK_HDMI_AUDIO_ENABLE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_HDMI_AUDIO_ENABLE, unsigned int)
|
|
|
|
#define DRM_IOCTL_MTK_HDMI_AUDIO_CONFIG DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_MTK_HDMI_AUDIO_CONFIG, unsigned int)
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#define DRM_IOCTL_MTK_HDMI_GET_CAPABILITY DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_MTK_HDMI_GET_CAPABILITY, unsigned int)
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#define MTK_DRM_ADVANCE
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#define MTK_DRM_FORMAT_DIM fourcc_code('D', ' ', '0', '0')
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#endif /* _UAPI_MEDIATEK_DRM_H */
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