471 lines
13 KiB
C
471 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: CY Huang <cy_huang@richtek.com>
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*/
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#ifndef __RT5509_H
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#define __RT5509_H
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#include <linux/atomic.h>
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#include <linux/semaphore.h>
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#include <mt-plat/rt-regmap.h>
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#define RT5509_DEVICE_NAME "rt5509"
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#define RT5509_DRV_VER "1.0.14_M"
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#ifdef CONFIG_RT_REGMAP
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#define RT5509_SIMULATE_DEVICE 0
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#if RT5509_SIMULATE_DEVICE
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int rt5509_calculate_offset(int reg);
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int rt5509_calculate_total_size(void);
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#endif /* #if RT5509_SIMULATE_DEVICE */
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#else
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#define RT5509_SIMULATE_DEVICE 0
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#endif /* #ifdef CONFIG_RT_REGMAP */
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enum {
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RT5509_CHIP_REVB = 0,
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RT5509_CHIP_REVC = 2,
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RT5509_CHIP_REVD,
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};
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enum {
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RT5509_CFG_GENERAL,
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RT5509_CFG_BOOSTCONV,
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RT5509_CFG_SPEAKERPROT,
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RT5509_CFG_SAFEGUARD,
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RT5509_CFG_EQ,
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RT5509_CFG_BEW,
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RT5509_CFG_DCR,
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RT5509_CFG_MBDRC,
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RT5509_CFG_ALC,
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RT5509_CFG_MAX,
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};
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struct rt5509_proprietary_param {
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u8 *cfg[RT5509_CFG_MAX];
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u32 cfg_size[RT5509_CFG_MAX];
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};
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struct rt5509_pdata {
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struct rt5509_proprietary_param *p_param;
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};
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struct rt5509_calib_classdev {
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struct device *dev;
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uint32_t n20db;
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uint32_t n15db;
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uint32_t n10db;
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uint32_t gsense_otp;
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uint32_t rspk;
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uint32_t dcr_offset;
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uint32_t rapp;
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int32_t rspkmin;
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int32_t rspkmax;
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int32_t alphaspk;
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int (*trigger_read)(struct rt5509_calib_classdev *calib_dev);
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int (*trigger_write)(struct rt5509_calib_classdev *calib_dev);
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int (*trigger_calculation)(struct rt5509_calib_classdev *calib_dev);
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};
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struct rt5509_chip {
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struct i2c_client *i2c;
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struct device *dev;
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struct rt5509_pdata *pdata;
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struct snd_soc_component *component;
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struct platform_device *pdev;
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struct rt5509_calib_classdev calib_dev;
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struct rt_regmap_device *rd;
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#if RT5509_SIMULATE_DEVICE
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void *sim;
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#endif /* #if RT5509_SIMULATE_DEVICE */
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struct semaphore io_semaphore;
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atomic_t power_count;
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u8 chip_rev;
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u8 mode_store;
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u8 func_en;
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u8 spk_prot_en;
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u8 alc_gain;
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u8 alc_min_gain;
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u8 classd_gain_store;
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u8 pgain_gain_store;
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u8 sig_gain_store;
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u16 sig_max_store;
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u16 pilot_freq;
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u8 recv_spec_set:1;
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u8 bypass_dsp:1;
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u8 calibrated:1;
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u8 tdm_mode:1;
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u8 rlr_func:1;
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int dev_cnt;
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};
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/* RT5509_REGISTER_LIST */
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#define RT5509_REG_CHIPREV 0x00
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#define RT5509_REG_EVENTINFO 0x01
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#define RT5509_REG_DMGFLAG 0x02
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#define RT5509_REG_CHIPEN 0x03
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#define RT5509_REG_AUDFMT 0x04
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#define RT5509_REG_AUDSR 0x05
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#define RT5509_REG_I2SSEL 0x06
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#define RT5509_REG_I2SDOLRSEL 0x07
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#define RT5509_REG_I2SDOSEL 0x08
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#define RT5509_REG_FUNCEN 0x09
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#define RT5509_REG_CLIP_THR 0x10
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#define RT5509_REG_CLIP_CTRL 0x11
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#define RT5509_REG_CLIP_SLOPE 0x12
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#define RT5509_REG_CLIP_VOMIN 0x13
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#define RT5509_REG_CLIP_SIGMAX 0x14
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#define RT5509_REG_AMPCONF 0x15
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#define RT5509_REG_DACRNKGAIN 0x16
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#define RT5509_REG_SAMPOFFS 0x17
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#define RT5509_REG_SAMPCONF 0x18
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#define RT5509_REG_DAGAIN 0x19
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#define RT5509_REG_FFGAIN 0x1A
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#define RT5509_REG_VBATGAIN 0x1B
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#define RT5509_REG_RLDCOEF1 0x1C
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#define RT5509_REG_RLDCOEF2 0x1D
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#define RT5509_REG_BST_MODE 0x1E
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#define RT5509_REG_BST_TH1 0x1F
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#define RT5509_REG_BST_TH2 0x20
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#define RT5509_REG_BST_TH3 0x21
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#define RT5509_REG_BST_CONF1 0x22
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#define RT5509_REG_BST_SIG_GAIN 0x23
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#define RT5509_REG_BST_CONF2 0x24
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#define RT5509_REG_BST_CONF3 0x25
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#define RT5509_REG_OCPOTPEN 0x26
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#define RT5509_REG_IDAC1TST 0x27
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#define RT5509_REG_IDAC2TST 0x28
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#define RT5509_REG_IDAC3TST 0x29
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#define RT5509_REG_IDACTSTEN 0x2A
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#define RT5509_REG_CCMAX 0x2B
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#define RT5509_REG_OCPMAX 0x2C
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#define RT5509_REG_INTERRUPT 0x2D
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#define RT5509_REG_INTRMASK 0x2E
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#define RT5509_REG_DEGLITCH 0x2F
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#define RT5509_REG_SICRTNSTHACT 0x30
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#define RT5509_REG_TIMEDET 0x31
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#define RT5509_REG_TDELAY 0x32
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#define RT5509_REG_TATKSEL 0x33
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#define RT5509_REG_TREL 0x34
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#define RT5509_REG_THOLDREL 0x35
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#define RT5509_REG_STHLMT 0x38
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#define RT5509_REG_XTHLMT 0x39
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#define RT5509_REG_STHALC 0x3A
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#define RT5509_REG_XTHALC 0x3B
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#define RT5509_REG_INITUDT 0x3C
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#define RT5509_REG_UDT 0x3D
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#define RT5509_REG_DNHALFT 0x3E
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#define RT5509_REG_ALCGAIN 0x3F
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#define RT5509_REG_ADAPTCONF 0x40
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#define RT5509_REG_INITIMPLDMU 0x41
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#define RT5509_REG_IMPLDMU 0x42
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#define RT5509_REG_GPILOT 0x43
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#define RT5509_REG_PILOTEN 0x44
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#define RT5509_REG_PILOTNISENSE 0x45
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#define RT5509_REG_ISENSEGAIN 0x46
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#define RT5509_REG_RAPP 0x47
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#define RT5509_REG_DCR_MAX 0x48
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#define RT5509_REG_DCR_KD 0x49
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#define RT5509_REG_DCR_KP 0x4A
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#define RT5509_REG_DCR_KI 0x4B
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#define RT5509_REG_INITDCRIDMU 0x4C
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#define RT5509_REG_DCRIDMU 0x4D
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#define RT5509_REG_CALIB_DCR 0x4E
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#define RT5509_REG_CALIB_BL 0x4F
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#define RT5509_REG_CALIB_CTRL 0x50
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#define RT5509_REG_CALIB_REQ 0x51
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#define RT5509_REG_CALIB_GAIN 0x52
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#define RT5509_REG_CALIB_OUT0 0x53
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#define RT5509_REG_CALIB_OUT1 0x54
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#define RT5509_REG_XTHLMTDAM 0x55
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#define RT5509_REG_RMAXDAM 0x56
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#define RT5509_REG_TSCALEDAM 0x57
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#define RT5509_REG_RECOVERT 0x58
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#define RT5509_REG_SETRESFREQ 0x59
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#define RT5509_REG_GETRESFREQ 0x5A
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#define RT5509_REG_VOLCTL 0x5B
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#define RT5509_REG_VOLUME 0x5C
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#define RT5509_REG_CALIB_OUTX 0x5D
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#define RT5509_REG_CALIB_OUTY 0x5E
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#define RT5509_REG_BQ1 0x60
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#define RT5509_REG_BQ2 0x61
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#define RT5509_REG_BQ3 0x62
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#define RT5509_REG_BQ4 0x63
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#define RT5509_REG_BQ5 0x64
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#define RT5509_REG_BQ6 0x65
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#define RT5509_REG_BQ7 0x66
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#define RT5509_REG_BQ8 0x67
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#define RT5509_REG_BQ9 0x68
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#define RT5509_REG_BQ10 0x69
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#define RT5509_REG_VBBQ1 0x6A
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#define RT5509_REG_VBBQ2 0x6B
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#define RT5509_REG_VBBQ3 0x6C
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#define RT5509_REG_VBBQ4 0x6D
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#define RT5509_REG_VBBQ5 0x6E
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#define RT5509_REG_VBBQ6 0x6F
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#define RT5509_REG_VBBQ7 0x70
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#define RT5509_REG_VBBQ8 0x71
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#define RT5509_REG_VBBQ9 0x72
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#define RT5509_REG_VBFCN 0x73
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#define RT5509_REG_VBGAIN1 0x74
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#define RT5509_REG_VBGAIN2 0x75
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#define RT5509_REG_VBGAIN3 0x76
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#define RT5509_REG_VBGAIN4 0x77
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#define RT5509_REG_VBGAIN5 0x78
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#define RT5509_REG_VBGAIN6 0x79
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#define RT5509_REG_VBGAIN7 0x7A
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#define RT5509_REG_VBGAIN8 0x7B
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#define RT5509_REG_VBGAIN9 0x7C
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#define RT5509_REG_VBGAIN10 0x7D
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#define RT5509_REG_SLOPCONST 0x7E
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#define RT5509_REG_BWCOEFF 0x7F
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#define RT5509_REG_SWRESET 0x80
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#define RT5509_REG_SPKGAIN 0x81
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#define RT5509_REG_DSPKCONF1 0x82
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#define RT5509_REG_DSPKCONF2 0x83
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#define RT5509_REG_DSPKCONF3 0x84
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#define RT5509_REG_DSPKCONF4 0x85
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#define RT5509_REG_DSPKVMID 0x86
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#define RT5509_REG_DSPKZCBOOST 0x87
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#define RT5509_REG_ISENSE_CTRL 0x88
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#define RT5509_REG_DIMADC 0x89
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#define RT5509_REG_DSPKEN1 0x8A
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#define RT5509_REG_VBATDATA 0x8B
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#define RT5509_REG_VTHRMDATA 0x8C
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#define RT5509_REG_VBATSENSE 0x8D
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#define RT5509_REG_IDACTSTNINFO 0x8E
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#define RT5509_REG_IDACBOOST 0x8F
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#define RT5509_REG_DSPKEN2 0x90
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#define RT5509_REG_DSPKIBCONF1 0x91
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#define RT5509_REG_DSPKIBCONF2 0x92
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#define RT5509_REG_DSPKIBCONF3 0x93
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#define RT5509_REG_DSPKCONF5 0x94
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#define RT5509_REG_DSPKCONF6 0x95
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#define RT5509_REG_OVPUVPCTRL 0x96
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#define RT5509_REG_PLLCONF1 0x97
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#define RT5509_REG_PLLCONF2 0x98
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#define RT5509_REG_PLLCONF3 0x99
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#define RT5509_REG_PLLCONF4 0x9A
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#define RT5509_REG_PLLINFO 0x9B
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#define RT5509_REG_PLLDIVISOR 0x9C
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#define RT5509_REG_ZCCONF 0x9D
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#define RT5509_REG_DCADJ 0x9E
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#define RT5509_REG_I2CBCKLRCKCONF 0x9F
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#define RT5509_REG_TDEN 0xA0
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#define RT5509_REG_ALPHACONF 0xA1
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#define RT5509_REG_SPKRPTSEL 0xA2
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#define RT5509_REG_SPKRPT 0xA3
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#define RT5509_REG_NDELAY 0xA4
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#define RT5509_REG_DELAYRES 0xA5
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#define RT5509_REG_PHI1 0xA6
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#define RT5509_REG_PHI2 0xA7
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#define RT5509_REG_PHI3 0xA8
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#define RT5509_REG_PHI4 0xA9
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#define RT5509_REG_PHI5 0xAA
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#define RT5509_REG_ADAPTB0 0xAB
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#define RT5509_REG_ADAPTB1 0xAC
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#define RT5509_REG_ADAPTB2 0xAD
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#define RT5509_REG_ADAPTB3 0xAE
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#define RT5509_REG_ADAPTB4 0xAF
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#define RT5509_REG_ADAPTB5 0xB0
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#define RT5509_REG_COEFSIERA 0xB1
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#define RT5509_REG_COEFHPF 0xB2
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#define RT5509_REG_MIMATC_CTRL 0xB3
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#define RT5509_REG_TDM_CTRL 0xB4
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#define RT5509_REG_ECO_CTRL 0xB5
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#define RT5509_REG_BSTTM 0xB8
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#define RT5509_REG_ALCMINGAIN 0xB9
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#define RT5509_REG_RESVECO0 0xBA
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#define RT5509_REG_OTPCONF 0xC0
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#define RT5509_REG_OTPADDR 0xC1
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#define RT5509_REG_OTPDIN 0xC2
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#define RT5509_REG_VBG_TRIM 0xC3
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#define RT5509_REG_VTEMP_TRIM 0xC4
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#define RT5509_REG_TCOEFF 0xC5
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#define RT5509_REG_SPSCONF 0xC6
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#define RT5509_REG_SPSTHR 0xC7
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#define RT5509_REG_VTHERMBATEN 0xC8
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#define RT5509_REG_DBGADS 0xC9
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#define RT5509_REG_TESTDAC 0xCA
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#define RT5509_REG_SPKDCS 0xCB
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#define RT5509_REG_MSKFLAG 0xCC
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#define RT5509_REG_DRCMINGAIN 0xCF
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#define RT5509_REG_DRC_SEL 0xD0
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#define RT5509_REG_DRC_ATTACK 0xD1
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#define RT5509_REG_DRC_PARAM 0xD2
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#define RT5509_REG_DRCBQ1 0xD3 /* Limiter1 */
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#define RT5509_REG_DRCBQ2 0xD4 /* Limiter2 */
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#define RT5509_REG_DRCBQ3 0xD5 /* High1 */
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#define RT5509_REG_DRCBQ4 0xD6 /* High2 */
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#define RT5509_REG_DRCBQ5 0xD7 /* Mid1 */
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#define RT5509_REG_DRCBQ6 0xD8 /* Mid2 */
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#define RT5509_REG_DRCBQ7 0xD9 /* Mid3 */
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#define RT5509_REG_DRCBQ8 0xDA /* Mid4 */
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#define RT5509_REG_DRCBQ9 0xDB /* Low1 */
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#define RT5509_REG_DRCBQ10 0xDC /* Low2 */
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#define RT5509_REG_DRCBQ11 0xDD /* Sub1 */
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#define RT5509_REG_DRCBQ12 0xDE /* Sub2 */
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#define RT5509_REG_DRCEN 0xDF
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#define RT5509_REG_MTPFLOW1 0xE1
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#define RT5509_REG_MTPFLOW2 0xE2
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#define RT5509_REG_MTPFLOW3 0xE3
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#define RT5509_REG_MTPFLOW4 0xE4
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#define RT5509_REG_MTPFLOW5 0xE5
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#define RT5509_REG_MTPFLOW6 0xE6
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#define RT5509_REG_MTPFLOW7 0xE7
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#define RT5509_REG_MTPFLOW8 0xE8
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#define RT5509_REG_MTPFLOW9 0xE9
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#define RT5509_REG_MTPFLOWA 0xEA
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#define RT5509_REG_MTPFLOWB 0xEB
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#define RT5509_REG_MTPFLOWC 0xEC
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#define RT5509_REG_MTPFLOWD 0xED
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#define RT5509_REG_MTPFLOWE 0xEE
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#define RT5509_REG_MTPFLOWF 0xEF
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#define RT5509_REG_TESTMODE1 0xF0
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#define RT5509_REG_RAMIND1 0xF1
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#define RT5509_REG_RAMIND2 0xF2
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#define RT5509_REG_SCANMODE 0xF3
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#define RT5509_REG_CLKEN1 0xF4
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#define RT5509_REG_CLKEN2 0xF5
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#define RT5509_REG_PADDRV 0xF6
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#define RT5509_REG_TESTMODE2 0xF7
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#define RT5509_REG_SLEWRATE1 0xF8
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#define RT5509_REG_SLEWRATE2 0xF9
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#define RT5509_REG_BIASRESISTOR 0xFA
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#define RT5509_REG_SPKDRV 0xFB
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#define RT5509_REG_BLOCKREF1 0xFC
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#define RT5509_REG_BLOCKREF2 0xFD
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#define RT5509_REG_BIASCURRENT 0xFE
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#define RT5509_REG_BIASOPTION 0xFF
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#define RT5509_MAX_REGS 0x100
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/* RT5509_REG_CHIPREV: 0x00 */
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#define RT5509_CHIPID_MASK 0xF0
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#define RT5509_CHIP_ID 0xE0
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#define RT5509_CHIPREV_MASK 0x0F
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#define RT5509_CHIPREV_SHFT 0
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/* RT5509_REG_EVENTINFO: 0x01 */
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#define RT5509_BCKLOCK_STATSHFT 7
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#define RT5509_PLLLOCK_STATSHFT 6
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#define RT5509_BATUV_STATSHFT 5
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#define RT5509_AMPOV_STATSHFT 4
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#define RT5509_AMPOC_STATSHFT 3
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#define RT5509_AMPOT_STATSHFT 2
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#define RT5509_BSTOC_STATSHFT 1
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#define RT5509_BSTOT_STATSHFT 0
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/* RT5509_REG_CHIPEN: 0x03 */
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#define RT5509_TRIWAVE_ENMASK 0x20
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#define RT5509_SPKAMP_ENMASK 0x08
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#define RT5509_SPKAMP_ENSHFT 3
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#define RT5509_SPKMUTE_ENMASK 0x04
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#define RT5509_SPKPROT_ENMASK 0x02
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#define RT5509_SPKPROT_ENSHFT 1
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#define RT5509_CHIPPD_ENMASK 0x01
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/* RT5509_REG_AUDFMT: 0x04 */
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enum {
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RT5509_DSP_MODEA = 0,
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RT5509_DSP_MODEB,
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};
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#define RT5509_DSPMODE_MASK 0x10
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#define RT5509_DSPMODE_SHFT 4
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enum {
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RT5509_AUDFMT_I2S = 0,
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RT5509_AUDFMT_LEFTJ,
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RT5509_AUDFMT_RIGHTJ,
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};
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#define RT5509_AUDFMT_MASK 0x0C
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#define RT5509_AUDFMT_SHFT 2
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enum {
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RT5509_AUDBIT_24 = 0,
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RT5509_AUDBIT_20,
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RT5509_AUDBIT_18,
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RT5509_AUDBIT_16,
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};
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#define RT5509_AUDBIT_MASK 0x03
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#define RT5509_AUDBIT_SHFT 0
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/* RT5509_REG_AUDSR: 0x05 */
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enum {
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RT5509_BCKMODE_32FS = 0,
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RT5509_BCKMODE_48FS,
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RT5509_BCKMODE_64FS,
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};
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#define RT5509_BCKMODE_MASK 0x18
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#define RT5509_BCKMODE_SHFT 3
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enum {
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RT5509_SRMODE_8K = 0,
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RT5509_SRMODE_12K,
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RT5509_SRMODE_16K,
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RT5509_SRMODE_24K,
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RT5509_SRMODE_32K,
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RT5509_SRMODE_48K,
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RT5509_SRMODE_96K,
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RT5509_SRMODE_192K,
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};
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#define RT5509_SRMODE_MASK 0x07
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#define RT5509_SRMODE_SHFT 0
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|
|
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/* RT5509_REG_I2SSEL: 0x06 */
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#define RT5509_I2SLRSEL_SHFT 2
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#define RT5509_I2SSEL_SHFT 0
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|
|
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/* RT5509_REG_FUNCEN: 0x09 */
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#define RT5509_LMTEN_SHFT 5
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|
#define RT5509_ALCEN_SHFT 4
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#define RT5509_MBDRCEN_SHFT 3
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#define RT5509_BEWEN_SHFT 2
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|
#define RT5509_HPFEN_SHFT 1
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#define RT5509_BQEN_SHFT 0
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|
|
|
/* RT5509_REG_CLIP_CTRL : 0x11 */
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|
#define RT5509_CLIPEN_SHFT 7
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|
|
|
/* RT5509_REG_BST_MODE: 0x1E */
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|
#define RT5509_BSTMODE_SHFT 0
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|
#define RT5509_BSTMODE_MASK 0x03
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|
|
|
/* RT5509_REG_SWRESET: 0x80 */
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|
#define RT5509_SWRST_MASK 0x80
|
|
|
|
/* RT5509_REG_SPKGAIN: 0x81 */
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|
#define RT5509_BSTGAIN_SHFT 5
|
|
#define RT5509_POSTPGAGAIN_SHFT 0
|
|
|
|
/* RT5509_REG_DSPKCONF1: 0x82 */
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|
#define RT5509_PREPGAGAIN_SHFT 0
|
|
|
|
/* RT5509_REG_DSPKVMID: 0x86 */
|
|
#define RT5509_VMID_ENMASK 0x80
|
|
|
|
/* RT5509_REG_DSPKEN1: 0x8A */
|
|
#define RT5509_BUF_ENMASK 0x80
|
|
#define RT5509_BIAS_ENMASK 0x40
|
|
|
|
/* RT5509_REG_DSPKCONF5: 0x94 */
|
|
#define RT5509_VBG_ENMASK 0x40
|
|
|
|
/* RT5509_REG_TDM_CTRL: 0xB4 */
|
|
#define RT5509_TDM_ENMASK 0x08
|
|
|
|
/* RT5509_REG_CLKEN1: 0xF4 */
|
|
#define RT5509_CLKEN1_MASK 0xFF
|
|
|
|
/* RT5509_REG_CLKEN2: 0xF5 */
|
|
#define RT5509_CLKEN2_MASK 0x03
|
|
|
|
struct rt_regmap_device *rt5509_regmap_register(
|
|
struct rt_regmap_fops *regmap_ops,
|
|
struct device *parent, void *client, void *drvdata);
|
|
int rt5509_calib_create(struct rt5509_chip *chip);
|
|
void rt5509_calib_destroy(struct rt5509_chip *chip);
|
|
int rt5509_i2c_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id);
|
|
int rt5509_i2c_remove(struct i2c_client *client);
|
|
void rt5509_i2c_shutdown(struct i2c_client *client);
|
|
|
|
#endif /* #ifndef __RT5509_H */
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