34 lines
1,011 B
Plaintext
34 lines
1,011 B
Plaintext
Hisilicon Hip06 Low Pin Count device
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Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
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provides I/O access to some legacy ISA devices.
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Hip06 is based on arm64 architecture where there is no I/O space. So, the
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I/O ports here are not CPU addresses, and there is no 'ranges' property in
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LPC device node.
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Required properties:
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- compatible: value should be as follows:
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(a) "hisilicon,hip06-lpc"
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(b) "hisilicon,hip07-lpc"
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- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
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- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
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- reg: base memory range where the LPC register set is mapped.
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Note:
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The node name before '@' must be "isa" to represent the binding stick to the
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ISA/EISA binding specification.
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Example:
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isa@a01b0000 {
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compatible = "hisilicon,hip06-lpc";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x0 0xa01b0000 0x0 0x1000>;
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ipmi0: bt@e4 {
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compatible = "ipmi-bt";
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device_type = "ipmi";
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reg = <0x01 0xe4 0x04>;
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};
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};
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