63 lines
1.9 KiB
Plaintext
63 lines
1.9 KiB
Plaintext
Mediatek DSI Device
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===================
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The Mediatek DSI function block is a sink of the display subsystem and can
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drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
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channel output.
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Required properties:
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- compatible: "mediatek,<chip>-dsi"
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the supported chips are mt2701 and mt8173.
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- clock-names: must contain "engine", "digital", and "hs"
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- phys: phandle link to the MIPI D-PHY controller.
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- phy-names: must contain "dphy"
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- port: Output port node with endpoint definitions as described in
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Documentation/devicetree/bindings/graph.txt. This port should be connected
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to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
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MIPI TX Configuration Module
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============================
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The MIPI TX configuration module controls the MIPI D-PHY.
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Required properties:
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- compatible: "mediatek,<chip>-mipi-tx"
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the supported chips are mt2701 and mt8173.
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- reg: Physical base address and length of the controller's registers
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- clocks: PLL reference clock
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- clock-output-names: name of the output clock line to the DSI encoder
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- #clock-cells: must be <0>;
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- #phy-cells: must be <0>.
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Example:
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mipi_tx0: mipi-dphy@10215000 {
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compatible = "mediatek,mt8173-mipi-tx";
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reg = <0 0x10215000 0 0x1000>;
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clocks = <&clk26m>;
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clock-output-names = "mipi_tx0_pll";
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#clock-cells = <0>;
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#phy-cells = <0>;
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};
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dsi0: dsi@1401b000 {
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compatible = "mediatek,mt8173-dsi";
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reg = <0 0x1401b000 0 0x1000>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
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<&mipi_tx0>;
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clock-names = "engine", "digital", "hs";
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phys = <&mipi_tx0>;
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phy-names = "dphy";
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port {
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dsi0_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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